Jean-Michel Portal

TL;DR: A nonvolatile memory including a plurality of elementary cells, each cell including a first programmable-resistance storage element connected between first and second nodes of the cell, a first access transistor coupling the second node to a third node of cell, and a second access transistor coupled the second vertex to a fourth vertex of cell as discussed by the authors.

TL;DR: In this article, a two-transistor/two-resistor memory architecture employing a precharge sense amplifier is proposed, where the weight value can be extracted in a single sense operation.

TL;DR: In this paper, the authors propose a low energy binarized neural network, which employs brain-inspired concepts, while retaining energy benefits from digital electronics, using hafnium oxide resistive memory integrated in the back end of line of a 130 nanometer CMOS process.

TL;DR: In this article, a non-volatile memory consisting of selection transistors is proposed, where each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulators.

TL;DR: This work presents a manufactured differential hybrid CMOS/RRAM memory architecture suitable for neural network implementation that functions without formal ECC, and shows that using low-energy but error-prone programming conditions only slightly reduces network accuracy.