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Jean-Michel Portal

Researcher at Centre national de la recherche scientifique

Publications -  145
Citations -  2335

Jean-Michel Portal is an academic researcher from Centre national de la recherche scientifique. The author has contributed to research in topics: Resistive random-access memory & Artificial neural network. The author has an hindex of 25, co-authored 136 publications receiving 2047 citations. Previous affiliations of Jean-Michel Portal include Alternatives & Aix-Marseille University.

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Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks

TL;DR: In this article, a model of the weak RESET process in hafnium oxide RRAM is presented and integrated into the PyTorch deep learning framework for training Binarized Neural Networks for handwritten digit recognition and object classification.
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Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy

TL;DR: In this paper , a 32 × 32 in-memory computing system, fabricated in a hybrid complementary metaloxide-semiconductor (CMOS)/hafnium oxide technology, was used to classify heart arrhythmia from electrocardiogram.
Proceedings ArticleDOI

Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory

TL;DR: A new concept for improving efficiency of a charge pump system is presented, based on a set of elementary charge pumps connected in parallel in addition to the detection of the number of memory cells to be programmed at the same time.
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1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

TL;DR: In this article , a 1S1R (1 Selector 1 Resistor) device composed of a HfO2-based OxRAM memory stacked on a GeSeSb•N-based ovonic threshold switch (OTS) back-end selector is proposed for high-density binarized SNNs (BSNNs) synaptic weight hardware implementation.
Proceedings ArticleDOI

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations

TL;DR: This work demonstrates experimentally an RRAM-based IMC logic concept with strong resilience to RRAM variability, even after one million endurance cycles, a new milestone for RRAM in-memory logic.