International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Natural organic matter removal by coagulation during drinking water treatment: A review

The resistance switching behaviour of several materials has recently attracted considerable attention for its application in non-volatile memory (NVM) devices, popularly described as resistive random access memories (RRAMs). RRAM is a type of NVM that uses a material(s) that changes the resistance when a voltage is applied. Resistive switching phenomena have been observed in many oxides: (i) binary transition metal oxides (TMOs), e.g. TiO(2), Cr(2)O(3), FeO(x) and NiO; (ii) perovskite-type complex TMOs that are variously functional, paraelectric, ferroelectric, multiferroic and magnetic, e.g. (Ba,Sr)TiO(3), Pb(Zr(x) Ti(1-x))O(3), BiFeO(3) and Pr(x)Ca(1-x)MnO(3); (iii) large band gap high-k dielectrics, e.g. Al(2)O(3) and Gd(2)O(3); (iv) graphene oxides. In the non-oxide category, higher chalcogenides are front runners, e.g. In(2)Se(3) and In(2)Te(3). Hence, the number of materials showing this technologically interesting behaviour for information storage is enormous. Resistive switching in these materials can form the basis for the next generation of NVM, i.e. RRAM, when current semiconductor memory technology reaches its limit in terms of density. RRAMs may be the high-density and low-cost NVMs of the future. A review on this topic is of importance to focus concentration on the most promising materials to accelerate application into the semiconductor industry. This review is a small effort to realize the ambitious goal of RRAMs. Its basic focus is on resistive switching in various materials with particular emphasis on binary TMOs. It also addresses the current understanding of resistive switching behaviour. Moreover, a brief comparison between RRAMs and memristors is included. The review ends with the current status of RRAMs in terms of stability, scalability and switching speed, which are three important aspects of integration onto semiconductors.

https://iopscience.iop.org/article/10.1088/0034-4885/75/7/076502/pdf

Emerging memories: resistive switching mechanisms and current status.

Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first revie...

https://www.tandfonline.com/doi/pdf/10.1080/23746149.2016.1259585

Neuromorphic computing using non-volatile memory

Polycyclic aromatic hydrocarbons (PAHs) are a large group of organic compounds with two or more fused aromatic rings. They have a relatively low solubility in water, but are highly lipophilic. Most of the PAHs with low vapour pressure in the air are adsorbed on particles. When dissolved in water or adsorbed on particulate matter, PAHs can undergo photodecomposition when exposed to ultraviolet light from solar radiation. In the atmosphere, PAHs can react with pollutants such as ozone, nitrogen oxides and sulfur dioxide, yielding diones, nitro- and dinitro-PAHs, and sulfonic acids, respectively. PAHs may also be degraded by some microorganisms in the soil. PAHs are widespread environmental contaminants resulting from incomplete combustion of organic materials. The occurrence is largely a result of anthropogenic emissions such as fossil fuel-burning, motor vehicle, waste incinerator, oil refining, coke and asphalt production, and aluminum production, etc. PAHs have received increased attention in recent years in air pollution studies because some of these compounds are highly carcinogenic or mutagenic. Eight PAHs (Car-PAHs) typically considered as possible carcinogens are: benzo(a)anthracene, chrysene, benzo(b)fluoranthene, benzo(k)fluoranthene, benzo(a)pyrene (B(a)P), dibenzo(a,h)anthracene, indeno(1,2,3-cd)pyrene and benzo(g,h,i)perylene. In particular, benzo(a)pyrene has been identified as being highly carcinogenic. The US Environmental Protection Agency (EPA) has promulgated 16 unsubstituted PAHs (EPA-PAH) as priority pollutants. Thus, exposure assessments of PAHs in the developing world are important. The scope of this review will be to give an overview of PAH concentrations in various environmental samples and to discuss the advantages and limitations of applying these parameters in the assessment of environmental risks in ecosystems and human health. As it well known, there is an increasing trend to use the behavior of pollutants (i.e. bioaccumulation) as well as pollution-induced biological and biochemical effects on human organisms to evaluate or predict the impact of chemicals on ecosystems. Emphasis in this review will, therefore, be placed on the use of bioaccumulation and biomarker responses in air, soil, water and food, as monitoring tools for the assessment of the risks and hazards of PAH concentrations for the ecosystem, as well as on its limitations.

/pdf/monitoring-of-environmental-exposure-to-polycyclic-aromatic-34edfn0ke5.pdf

Monitoring of environmental exposure to polycyclic aromatic hydrocarbons: a review

Resistive RAM variability monitoring using a ring oscillator based test chip

Cryptographic algorithms albeit mathematically
sure may have security breaches when implemented on hardware
chips. There are several ways to compromise their security, one
method is to analyze their electromagnetic (EM) emissions in
order to find secrets (cryptographic keys for example). This paper
proposes a proof of concept of a countermeasure against these
attacks, it is based on a chaotic oscillator coupled with an antenna
to blur the EM emissions of the chip. The objective is to generate
EM noise within the chip with an internal system in order to
make the secret information harder to extract. A testchip was
developed and tested in conditions as close as possible to real usecase
to prove the relevance of the concept. The EM field collected
while running the chip were superposed to AES (Advanced
Encryption Standard) emissions collected using a similar setup to
test the disturbing effect of the noise on a CPA, a classic attack to
retrieve AES keys. The experiment shows that it can effectively
increase the difficulty of finding the keys, proving that the basic
concept and the developed chip can be used as a countermeasure
for EM analysis attacks.

Electromagnetic Analysis Perturbation using Chaos Generator

Binarized Neural Networks, a recently discovered class of neural networks with minimal memory requirements and no reliance on multiplication, are a fantastic opportunity for the realization of compact and energy efficient inference hardware. However, such neural networks are generally not entirely binarized: their first layer remains with fixed point input. In this work, we propose a stochastic computing version of Binarized Neural Networks, where the input is also binarized. Simulations on the example of the Fashion-MNIST and CIFAR-10 datasets show that such networks can approach the performance of conventional Binarized Neural Networks. We evidence that the training procedure should be adapted for use with stochastic computing. Finally, the ASIC implementation of our scheme is investigated, in a system that closely associates logic and memory, implemented by Spin Torque Magnetoresistive Random Access Memory. This analysis shows that the stochastic computing approach can allow considerable savings with regards to conventional Binarized Neural networks in terms of area (62% area reduction on the Fashion-MNIST task). It can also allow important savings in terms of energy consumption, if we accept reasonable reduction of accuracy: for example a factor 2.1 can be saved, with the cost of 1.4% in Fashion-MNIST test accuracy. These results highlight the high potential of Binarized Neural Networks for hardware implementation, and that adapting them to hardware constrains can provide important benefits.

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

The invention relates to a non-volatile memory (1), comprising: selection transistors (3, 4) each comprising: a layer of semiconductor material with a channel zone (30) and conduction electrodes (32, 31); a gate stack (33) including a gate electrode (332) and a gate insulator (331); an isolation trench (60) between the transistors (3, 2); a memory structure (4, 5) of the RRAM type comprising: a control electrode (434); a dielectric layer (40) formed under the control electrode (434) and in the same material as the gate insulator, having a middle portion (401) vertically of the isolation trench (60) and ends (403, 402) extending vertically from conduction electrodes (32, 22), and configured to form conductive filaments. Said storage structure and said selection transistors are formed in the same pre-metallization layer.

Non-volatile memory promoting high integration density

The deployment of Edge AI requires energy-efficient hardware with a minimal memory footprint to achieve optimal performance. One approach to meet this challenge is the use of Binary Neural Networks (BNNs) based on non-volatile in-memory computing (IMC). In recent years, elegant ReRAM-based IMC solutions for BNNs have been developed, but they do not extend to the first layer of a BNN, which typically requires non-binary activations. In this paper, we propose a modified first layer architecture for BNNs that uses k-bit input images broken down into k binary input images with associated fully binary convolution layers and an accumulation layer with fixed weights of $2^{-1}, \ldots, 2^{-k}$. To further increase energy efficiency, we also propose reducing the number of operations by truncating 8-bit RGB pixel code to the 4 most significant bits (MSB). Our proposed architecture only reduces network accuracy by 0.28% on the CIFAR-10 task compared to a BNN baseline. Additionally, we propose a cost-effective solution to implement the weighted accumulation using successive charge sharing operations on an existing ReRAM-based IMC solution. This solution is validated through functional electrical simulations.

Jean-Michel Portal

Papers

Resistive RAM variability monitoring using a ring oscillator based test chip

Electromagnetic Analysis Perturbation using Chaos Generator

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

Non-volatile memory promoting high integration density

Binary ReRAM-based BNN first-layer implementation