J
Juan Pablo Duarte
Researcher at University of California, Berkeley
Publications - 55
Citations - 2414
Juan Pablo Duarte is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: BSIM & MOSFET. The author has an hindex of 23, co-authored 55 publications receiving 1965 citations. Previous affiliations of Juan Pablo Duarte include KAIST.
Papers
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Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors
TL;DR: In this article, the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters was investigated.
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Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor
Asif Islam Khan,Korok Chatterjee,Juan Pablo Duarte,Zhongyuan Lu,Angada B. Sachid,Sourabh Khandelwal,Ramamoorthy Ramesh,Chenming Hu,Sayeef Salahuddin +8 more
TL;DR: In this paper, the authors report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs with gate length $L_{g}=100$ nm.
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Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors
TL;DR: In this article, a bulk current model for long-channel double-gate junctionless (DGJL) transistors was formulated using a depletion approximation, and an analytical expression was derived from the Poisson equation to find channel potential.
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A Full-Range Drain Current Model for Double-Gate Junctionless Transistors
TL;DR: In this article, a drain current model for long-channel double-gate junctionless transistors was derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions.
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Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate
TL;DR: In this paper, a silicon nanowire with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field effect transistor (FET).