Kerry Joseph Nagel

TL;DR: In this article, the authors developed a fully functional 64 Mb DDR3 ST-MRAM built on 90 nm CMOS technology, which is organized in an 8-bank configuration that can sustain 1.6 GigaTransfers/s.

TL;DR: In this article, the authors describe a fully functional 1 Gb standalone spin-transfer torque magnetoresistive random access memory (STT-MRAM) integrated on 28 nm CMOS and based on perpendicular magnetic tunnel junctions.

TL;DR: An unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array with full array functionality, process uniformity and reliability, and 10 years data retention at 125C with extended endurance to ∼ 107 cycles is presented.

TL;DR: Key properties for commercial ST-MRAM circuits are reviewed, the challenges to achieving the many performance and scaling goals that are being addressed in current development around the world are discussed, recent results in the field are presented, and first results from a new, fully-functional 64Mb, DDR3, ST- MRAM circuit are presented.

TL;DR: An overview of important features for reliable and manufacturable ST-MRAM as well as new results in two areas: pMTJ arrays with data retention sufficient for programming before 260°C wave solder, and performance of a 256Mb, DDR3 ST- MRAM product chip.