Showing papers by "N. Balasubramanian published in 2008"

Silicon nanowire sensor array using top–down CMOS technology

Abstract: The paper elaborates the silicon nanowire (SiNW) arrays fabrication using standard CMOS compatible technologies (top–down) with each array consisting of 100 wires, which are individually electrically measurable for their conductance and facilitating statistical analysis. To facilitate real-time analysis, the arrays are integrated with micro-fluidics for the delivery of various chemicals for surface modification, buffer solutions, bio-molecules/analytes, etc. The silicon nanowires are also presented as nano-temperature sensors in two configurations, i.e. as resistance temperature detector (RTD) and diode temperature detector (DTD) types. RTD type sensors have shown temperature coefficient of resistance (TCR) values ∼7500 ppm/K which are enhanced beyond 10,000 ppm/K by the application of back-bias. DTD type sensors using nanowires have recorded more than one order variation in reverse-bias current, in the temperature range of 293–373 K. Both the types of nano-temperature sensors are highly sensitive and can be integrated with other bio-chemical sensors in lab-on-chip devices. Nanowire array fabrication details in particular as nano-temperature sensor are elaborated here along with their characterization.

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

Abstract: This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 mus for programming and 1 ms for erasing at VGS = plusmn11 V with a threshold voltage shift "DeltaVTH" of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications.

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon $(\hbox{Si}_{1 - y}\hbox{C}_{y})$ Source and Drain Stressors With High Carbon Content

Abstract: Phosphorus in situ doped (Si1-yCy) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source and drain regions of double-gate -oriented (110)-sidewall FinFETs to induce tensile strain in the silicon channel. In situ doping removes the need for a high-temperature spike anneal for source/drain (S/D) dopant activation and thus preserves the carbon substitutionality in the SiC:P films as grown. A strain-induced enhancement of 15% and 22% was obtained for n-channel FinFETs with 1.7% and 2.1% carbon incorporated in the S/D, respectively.

A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET

Abstract: We report the integration of a new liner stressor comprising diamond-like carbon (DLC) film over a p-channel transistor. A high compressive stress of 6.5 GPa was achieved in a high-stress film with a thickness of 27 nm. A 74% enhancement in drive current was observed for the strained device with DLC liner as compared to a control device without DLC liner. Due to its much higher intrinsic stress value compared to conventional SiN films, a thinner DLC layer can induce comparable amount of stress in the transistor channel compared to a thicker SiN. The DLC material is a potential next-generation high-stress and low-permittivity liner stressor material suitable for application in transistors with aggressively scaled pitch dimensions.

Preparation of nanochain and nanosphere by self-assembly of gold nanoparticles

Abstract: A self-assembly method is demonstrated to link nanoparticles into nanostructure of nanochain or nanosphere. Gold nanoparticles were covered with capping molecules by forming Au–S bonds with thiol group at one terminate. Another terminating group, carboxylic acid, showed strong complex interaction with inorganic linker Zr4+ to form covalent complex bond. The different nanostructures were obtained by moving a balance between two opposite interactions, the linking interaction of Zr4+ and the electrostatic repulsive interaction of net surface charge. When the capping molecule with different chain length was used, the linked nanochain feature exhibited a tunable interdistance between the neighboring nanoparticles.

Spacer Removal Technique for Boosting Strain in n-Channel FinFETs With Silicon-Carbon Source and Drain Stressors

Abstract: A novel and low-cost spacer removal technique proved successful in further enhancing the IDsat performance of already strained n-channel trigate FinFETs with SiC source and drain (S/D) stressors. This extra enhancement is attributed to increased longitudinal tensile channel stress as a result of increased stress coupling efficiency from the SiC S/D stressors to the channel. The electrical results also establish that this extra enhancement will become even more significant as physical gate lengths are scaled down.

Pulsed Laser Annealing of Silicon-Carbon Source/Drain in MuGFETs for Enhanced Dopant Activation and High Substitutional Carbon Concentration

Abstract: We report for the first time, the use of pulsed laser annealing (PLA) on multiple-gate field-effect transistors (MuGFETs) with silicon-carbon (Si1-xCx) source and drain (S/D) for enhanced dopant activation and improved strain effects. Si1-xCx. S/D exposed to consecutive laser irradiations demonstrated superior dopant activation with a ~60% reduction in resistivity compared to rapid thermal annealed S/D. In addition, with the application of PLA on epitaxially grown Si0.99C0.01 substitutional carbon concentration Csub increased from 1.0% (as grown) to 1.21%. This is also significantly higher than the Csub of 0.71% for rapid thermal annealed Si0.99C0.01 S/D. With a higher strain and enhanced dopant activation, MuGFETs with laser annealed Si0.99C0.01 S/D show a ~53% drain-current improvement compared to MuGFETs with rapid thermal annealed Si0.99C0.01 S/D.

Fabrication of Thick Germanium-on-Insulator (GeOI) Substrates

Abstract: Fabrication of germanium-on-insulator (GeOI) substrates with a 160-nm-thick Ge layer is reported. Such thick GeOI substrates were fabricated by thermal intermixing and subsequent condensation of epitaxially grown high-Ge- content SiGe on Si-on-insulator (SOI) substrates. Transmission electron microscopy revealed that the GeOI layer was single crystalline. The high-resolution rocking curve and reciprocal lattice map obtained from X-ray diffraction measurements showed a relaxed GeOI. This was further confirmed by micro-Raman measurements, where the Ge-Ge optical phonon peak shift represented a nearly strain-free Ge layer. Using this methodology, GeOI substrates with Ge layers 120–160 nm thick have been fabricated with thickness variations of less than 4 nm across 200 mm wafers.

5 nm gate length Nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique

Abstract: We report the first demonstration of pure Ge source/drain (S/D) stressors (un embedded) on the ultra-narrow or ultra-thin Si S/D regions of Nanowire-FETs and UTB-FETs, compressively straining the channels to provide up to ~100% IDsat enhancement. Devices with 5 nm gate lengths were fabricated. In addition, we report a novel Melt-Enhanced Dopant (MeltED) diffusion and activation technique to form embedded Ge S/D stressor in the S/D regions of nanowire-FETs, boosting the channel strain even further, and achieving ~125% IDsat enhancement.

Diamond-Like Carbon (DLC) Liner: A New Stressor for P-Channel Multiple-Gate Field-Effect Transistors

Abstract: We report the first demonstration of a p-channel multiple-gate (trigate) FinFET with a liner stressor comprising diamond-like carbon (DLC) film. We also report on the detailed process that enables the adhesion of DLC with ultrahigh compressive stress on the three-dimension topology of the FinFET structure. The intrinsic compressive stress for the DLC film is 6 GPa, the highest ever reported for a liner stressor formed over a multiple-gate device structure or FinFET. A high stress-thickness product was successfully realized without film delamination. This leads to a very significant drive current boost for the FinFET with DLC liner stressor as compared to a control FinFET without the DLC liner.

Germanium Source and Drain Stressors for Ultrathin-Body and Nanowire Field-Effect Transistors

Abstract: Pure germanium (Ge) source and drain (S/D) stressors are integrated with ultrathin-body (UTB) and nanowire field-effect transistors (FETs). This is the first report of the integration of Ge S/D stressors in FETs. The Ge S/D stressors induce a large compressive stress in the channel, resulting in up to 80% IDsat enhancement in UTB-FETs. Electrical results further show that increased substrate compliance effects allow nanowire FETs to achieve even higher levels (96%) of strain-induced enhancement.

Strained Silicon Nanowire Transistors With Germanium Source and Drain Stressors

Abstract: We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.

Nickel-Aluminum Alloy Silicides with High Aluminum Content for Contact Resistance Reduction and Integration in n-Channel Field-Effect Transistors

Abstract: In this paper, we demonstrate the silicidation of Ni 1-x Al x alloy film with the highest Al concentration reported to date for reduced contact resistance (R con ) through process optimization. Successful formation of Ni 1-x Al x alloy silicide with the use of film that has an Al concentration as high as 51% is shown. The onset of agglomeration has been eliminated, and the silicide yields a 0.40 eV electron barrier height, which is one of the lowest reported for any nickel alloy film. Subsequently, the benefits of the film using the optimal annealing condition are further verified through an 18% saturation drive current IDsat enhancement in n-channel metal-oxide-semiconductor field-effect transistors with Ni 1-x Al x silicide compared to NiSi. In addition, this paper also elucidates the dependency of Ni 1-x Al x alloy silicide properties on Al concentration and the annealing conditions.

Integration of RF MEMS and CMOS IC on a Printed Circuit Board for a Compact RF System Application Based on Wafer Transfer

Abstract: In this paper, a novel platform technology for integrating radio-frequency microelectromechanical systems (RF-MEMS) and CMOS on a printed circuit board (PCB) is demonstrated. An RF-MEMS switch is constructed on top of a CMOS IC wafer. The stacked structure is subsequently transferred onto a PCB substrate (i.e., FR-4) by thermal compressive bonding, mechanical grinding, and wet removal of bulk silicon. The measurement of the fabricated RF-MEMS switch on the FR-4 substrate shows promising results. It has an insertion loss of 0.25 dB at 20 GHz and an isolation of 25 dB at 20 GHz. At the same time, the performance of CMOS is not degraded during the integration process; the drain current in the p-MOS transistor remained unchanged, whereas that in the n-MOS transistor showed a slight improvement after transfer. This technology is very useful for compact RF system on PCB material with low power consumption and high performance for wearable, wireless, and implantable device applications.

A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancement

Abstract: We report for the first time a new process technology for boosting the Ge content in SiGe source/drain (S/D) stressors to increase strain and performance levels in p-FETs. By laser-induced local melting and inter-mixing of an amorphous Ge layer with an underlying Si0.8Ge0.2 S/D region, a graded SiGe S/D stressor is formed upon recrystallization. Peak Ge content in the graded SiGe S/D is doubled over the as-grown film. Raman analysis confirmed the retention of high S/D strain levels due to the rapid non-equilibrium recrystallization process. The new process technology developed here employs several simple additional steps, including amorphous Ge deposition and laser anneal (LA). For a p-FET with Ge enriched S/D, 21% and 12% IDsat enhancement at a fixed IOFF of 2times10-8 A/mum is observed over control p-FETs with Si0.8Ge0.2 S/D formed by RTA and LA, respectively.

Etching of TiN-based gates for advanced complementary metal-oxide-semiconductor devices

Abstract: This article presents results of study and optimization of plasma etching of TiN and TiN-TaN gates for sub-45 mm CMOS technology. By design of experiment in decoupled plasma source using HBr/Cl2 plasma, etching parameters were established providing smooth post-etch surface.

Strained FinFETs with In-situ Doped Si 1-y C y Source and Drain Stressors: Performance Boost with Lateral Stressor Encroachment and High Substitutional Carbon Content

Abstract: In this paper, we report the first demonstration of n-channel FinFETs with in-situ doped silicon-carbon (Si1-yCy or SiC:P) source and drain (S/D) stressors. New key features incorporated in this work for performance enhancement includes record-high substitutional carbon concentration Csub of 2.1%, high in-situ phosphorus doping concentration in S/D, extended Pi -shaped S/D stressors that wrap around the Si fin for maximum lattice interaction, lateral stressor encroachment under the spacer for closer promixity to channel region for maximum channel stress as well as reduced S/D extension resistances.

Novel Extended-Pi Shaped Silicon-Germanium Source/Drain Stressors for Strain and Performance Enhancement in p-Channel Tri-Gate Fin-Type Field-Effect Transistor

Abstract: Strained p-channel tri-gate fin-type field-effect transistor (FinFET) with extended-Pi (eΠ) shaped SiGe source/drain (S/D) is demonstrated with enhanced drive current performance of 33% at a fixed drain induced barrier lowering (DIBL) over FinFET with Π-SiGe S/D. The eΠ S/D stressor structure can be easily formed by simply using a longer HF cleaning time prior to the growth of SiGe in the S/D regions. The longer HF cleaning step created a recess into the buried oxide which allows SiGe to be grown below the base of the Si fin at the S/D regions, providing additional strain to the channel. Enhancement of device performance was also found to increase with the decrease of fin width and this benefit aggressively scaled tri-gate FinFET for advance technology node.