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Navab Singh

Researcher at Agency for Science, Technology and Research

Publications -  355
Citations -  8869

Navab Singh is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Nanowire & CMOS. The author has an hindex of 44, co-authored 346 publications receiving 7946 citations. Previous affiliations of Navab Singh include Singapore Science Park & National University of Singapore.

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High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
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Silicon Nanowire Arrays for Label-Free Detection of DNA

TL;DR: The SiNW array biosensor described here is ultrasensitive, non-radioactive, and more importantly, label-free, and is of particular importance to the development of gene expression profiling tools and point-of-care applications.
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Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
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DNA sensing by silicon nanowire: charge layer distance dependence.

TL;DR: To provide a comprehensive understanding of the field effect in silicon nanowire (SiNW) sensors, a systematic approach to fine tune the distance of a charge layer by controlling the hybridization sites of DNA to the SiNW preimmobilized with peptide nucleic acid (PNA) capture probes.
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Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

TL;DR: In this paper, the authors presented a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology, which achieved high aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm.