Showing papers by "Pramod Kumar Tiwari published in 2019"

Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects

Abstract: In this paper, a surface potential-based drain current model is developed to explore the static and quasi-static performance of substrate-biased tri-gate junctionless field-effect-transistors (TGJLFETs). The effects of substrate bias voltage on surface potential, charge density, and drain current are analyzed. The 2-D Poisson’s equation is solved to obtain front and back surface potentials incorporating the effect of substrate bias voltage for a long-channel TGJLFET. The front and back surface potentials are subsequently utilized to obtain total conduction charge density and drain current. Further, short-channel and quantum mechanical corrections are incorporated in the model to use it for scaled devices. Moreover, the terminal charges calculated using Ward–Dutton’s charge partitioning scheme are utilized to model the transcapacitances and quasi-static drain current for TGJLFET. Further, an equivalent large-signal transient model of the device is implemented in SPICE using Verilog-A, and the transient behavior of inverter and ring oscillator circuits are simulated and studied. The models are validated using a 3-D Visual TCAD device simulator from Cogenda Pvt. Ltd.

Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFET s Using Substrate Bias Induced Effects

Abstract: This paper proposes the substrate bias voltage dependent subthreshold models of channel potential, threshold voltage, current, drain induced barrier lowering, and subthreshold swing for tri-gate silicon-on-insulator (SOI) MOSFET s (TG- MOSFET s). The substrate induced surface potential effect has also been included in the derived models. A quasi-three-dimensional (3-D) approach has been used to derive the minimum of channel potential, which is later used to derive models of threshold voltage, current, drain induced barrier lowering, and swing. The analytical results of TG-SOI MOSFET have been compared with the simulation results obtained from the Visual TCAD, a 3-D device simulator from Cogenda Pvt. Ltd.

An Insight Into Self-Heating Effects and Its Implications on Hot Carrier Degradation for Silicon-Nanotube-Based Double Gate-All-Around (DGAA) MOSFETs

Abstract: Silicon-Nanotube-based ultra-thin DGAA MOSFETs have been extensively studied for their superior immunity to short channel effects (SCEs) and better drive current capability; however, the reliability issues owing to self-heating effects (SHEs) and hot carrier injection (HCI) degradation are yet to be investigated systematically. In advanced non-planar device structures, an increase in power density due to ultra-scaled device dimensions can aggravate both the carrier heating as well as lattice heating. In this paper, 3-dimensional (3-D) electrothermal (ET) simulations using coupled hydrodynamic and thermodynamic transport models are performed to analyze the electrothermal behavior and SHEs in ultra-thin DGAA MOSFET. 3-D TCAD simulation parameters are calibrated with the data obtained from the literature. Through advanced 3-D ET simulations, we demonstrate that the device thermal contact resistance adversely influences both the carrier temperature as well as lattice temperature. The implication of SHE on the device output drive current reduction is also analyzed. The effective drive current method is used to observe the impact of SHE on the intrinsic delay of the device. Further, the performance of the device due to HCI is also highlighted. HCI significantly degrades the overall device performance leading to increased gate leakage current. Finally, the reliability issues induced by SHEs with on-chip ambient temperature variations have also been interpreted using Sentauras based TCAD simulator.

PIM1 kinase promotes gallbladder cancer cell proliferation via inhibition of proline-rich Akt substrate of 40 kDa (PRAS40)

Abstract: Gallbladder cancer (GBC) is a rare malignancy, associated with poor disease prognosis with a 5-year survival of only 20%. This has been attributed to late presentation of the disease, lack of early diagnostic markers and limited efficacy of therapeutic interventions. Elucidation of molecular events in GBC can contribute to better management of the disease by aiding in the identification of therapeutic targets. To identify aberrantly activated signaling events in GBC, tandem mass tag-based quantitative phosphoproteomic analysis of five GBC cell lines was carried out. Proline-rich Akt substrate 40 kDa (PRAS40) was one of the proteins found to be hyperphosphorylated in all the invasive GBC cell lines. Tissue microarray-based immunohistochemical labeling of phospho-PRAS40 (T246) revealed moderate to strong staining in 77% of the primary gallbladder adenocarcinoma cases. Regulation of PRAS40 activity by inhibiting its upstream kinase PIM1 resulted in a significant decrease in cell proliferation, colony forming and invasive ability of GBC cells. Our results support the role of PRAS40 phosphorylation in GBC cell survival and aggressiveness. This study also elucidates phospho-PRAS40 as a clinical marker in GBC and the role of PIM1 as a therapeutic target in GBC.

Drain current modelling of double gate-all-around (DGAA) MOSFETs

Abstract: Here, an analytical modelling of drain current is presented for double gate-all-around (DGAA) MOSFETs. A common feature in all the multi-gate (MG) MOSFETs is that the channel charge in the sub-threshold regime is proportional to the channel cross-sectional area; whereas, the inversion charges above threshold locate near the Si/SiO 2 interfaces and are proportional to the total gated perimeter of the channel body. This distinctive feature introduces the notion of equivalent charge and has been widely used to model the drain current of any arbitrary non-classical MOSFET architecture. The authors have extended the aforementioned quasi-approach to model the drain current of DGAA MOSFET. The total gated perimeter of DGAA MOSFET is mapped by the gated perimeter of two GAA MOSFETs with different radii for the calculation of surface inversion charges above threshold. The currents obtained from two GAA MOSFETs are summed up to obtain the current of DGAA MOSFET. I – V characteristics and transconductance of the device for various physical parameters are compared and analysed with the numerical simulation results obtained from Visual-TCAD of Cogenda Int.

A Proposal for an Electrostatic Doping-Assisted Electroabsorption Modulator for Intrachip Communication

Abstract: In this paper, we report a CMOS compatible novel penta-electrode charge-plasma diode-based optical electroabsorption modulator (EAM). The proposed integrated EAM is junctionless and employs electrostatic doping in the semiconductor to change its absorption coefficient. The proposed EAM has a vertical metal–insulator–semiconductor (MIS) and lateral metal–semiconductor (MS) junctions. Using this novel MIS–MS-based charge plasma diode, EAM with various lengths are designed on the standard 220-nm silicon-on-insulator (SOI) platform. The numerical simulations, using commercially available TCAD tools and mode solvers, are performed to estimate the performances of the proposed modulators. A couple of combinations of materials having different work functions are used as electrodes to realize this MIS–MS charge plasma diode and their performances are extensively studied. The results predict that 550 $\mu \text{m}$ -long EAM with electrodes made of palladium and aluminum offers ~ 3.4 dB of dynamic extinction ratio (ER). Approximately 8.1 dB of insertion loss (IL) will be introduced by the proposed EAM with a length of $550~\mu \text{m}$ . The proposed modulator is expected to provide a maximum of 30.3 GHz operating speed with 26.2 GHz of 3-dB electrooptic bandwidth. Also, the simulation result indicates that the maximum dynamic energy consumption for the proposed EAM is approximately 39.1 fJ/bit at 12.5-Gb/s data rate.

Physical Insight into Self-heating Effects in Ultrathin Junctionless Gate-All-Around FETs

Abstract: In advanced non-planar MOSFETs architecture, the reliability issue is the primary concern by most researchers due to aggravated local self-heating arising from the enhanced active power dissipation inside the device structure. In this work, 3-D quantum-corrected electrothermal (ET) simulation based analysis is performed to have an insight into the self-heating effect (SHE) in ultra-thin junctionless gate-all-around FETs. The effect of quantum confinement on the carrier distribution due to the ultra-thin channel region is also considered. Through coupled hydrodynamic and thermodynamic carriers transport models, we demonstrate the influence of SHE on the drive current capability, negative output conductance and reliability of the device structure. The ET simulation results also establish the fact that the thermal contact resistance (R th ) strongly influence the device lattice and carriers temperature and the overall performance of the device. Finally, the reliability issues or degradation mechanism of SHE with on-chip ambient temperature variations has also been investigated.

Compact Drain Current Model of Silicon-Nanotubebased Double Gate-All-Around (DGAA) MOSFETs Incorporating Short Channel Effects

Abstract: This paper reports a compact drain current model of silicon nanotube-based double gate all around (DGAA) MOSFET incorporating short channel effects (SCEs). The drain current equation is expressed as a function of charge density, which is derived using the unified surface potential expressions. Fermi-Dirac statistics, the 1-dimensional density of states and Gauss's law have been utilized to develop the analytical expressions of unified surface potentials and charge density. The proposed compact model also takes into account of quantum confinement effects which is significant in devices with the ultra-thin channel region. The SCEs such as velocity saturation effect, threshold voltage roll-off, DIBL, channel length modulation, velocity overshoot, and mobility degradation are well incorporated in the developed model in order to correctly predict the device output and transfer characteristics. Results obtained from the proposed compact drain current model have been validated with TCAD results obtained from the Sentauras device simulator.

Semianalytical Threshold Voltage Model of a Double-Gate Nanoscale RingFET for Terahertz Applications in Radiation-Hardened (Rad-Hard) Environments

Abstract: In this work, a recent device structure called double-gate (DG) nanoscale RingFET has been investigated by developing a computationally efficient foremost semianalytical threshold voltage model. Poisson’s equation has been solved using parabolic approximation to calculate surface channel potential, which has been further employed to formulate the threshold voltage of the device. This device comes under the category of edgeless transistor, which has a lot of scope in radiation harsh environment-based applications. A cutoff frequency of terahertz range up to 1.1 THz has been observed in this device, which makes it very useful for high-frequency applications. The proposed model results are extensively verified with the simulation data obtained with a three-dimensional technology computer-aided design (3D TCAD) simulator from SILVACO ATLAS™. Both the modeled and simulated results are found to be in good agreement.

Genotypic diversity of Mycobacterium tuberculosis isolates from North-Central Indian population.

Abstract: Background: Different strains of Mycobacterium tuberculosis (MTB) are known to have different epidemiological and clinical characteristics. Some of them are widely distributed and associated with d...

Temperature Dependence of Subthreshold Characteristics of Negative Capacitance Recessed-Source/Drain (NC R-S/D) SOI MOSFET

Abstract: This paper presents the subthreshold performance analysis of negative capacitance Recessed-Source/Drain SOI MOSFET (NC R-S/D SOI MOSFET). The effect of ferroelectric thickness on the subthreshold performance of NC R-S/D SOI MOSFET at given R-S/D thickness is studied and the same is compared with negative capacitance SOI MOSFET (NC SOI MOSFET). Device performance is also assessed at two different temperatures 300K and 340K to observe the device behavior at high temperatures. The parameters such as transfer characteristics, variation in subthreshold swing (SS) with drain current, the effect of ferroelectric thickness on the minimum subthreshold swing and the influence of negative capacitance on gate capacitance of the device are studied. The minimum subthreshold swing of 29mV/decade is achieved for NC R-S/D SOI MOSFET at 300K with a ferroelectric thickness of 5.5nm and recessed source/drain thickness of 10nm which is much lower than Boltzmann's limit (60mV/decade).

Investigation of Thermal Noise in Trigate Junctionless Transistor

Abstract: This paper presents a 3-D TCAD simulation based study of thermal noise in trigate junctionless field effect transistors (TG-JLFET). Thermal noise in JLFETs increases with channel conductivity, therefore, it is crucial to control the noise while maintaining a good conductivity of the device. This paper shows that variation in device parameters, like channel width, thickness and doping concentration, may be used to reduce thermal noise and optimize the device design for RF applications. Drain current thermal noise, induced gate noise and cross-correlation noise in TG-JLFET are studied through Sentaurus TCAD device simulator.

Analytical Modeling of Analog/RF Parameters for Trigate Junctionless Field Effect Transistor Incorporating Substrate Biasing Effects

Abstract: This paper develops analytical models for analog and RF parameters of trigate junctionless field effect transistor (TGJLFET) incorporating substrate voltage effects. Analog parameters like, transconductance, output conductance and transconductance generation factor are modeled using continuous drain current model of substrate biased TGJLFET. The charge partitioning scheme by Ward-Dutton is used to obtain the charges on device terminals. Further, these charge models are used to derive gate-to-source/drain/substrate capacitances and cut-off frequency. The paper demonstrates that applied substrate voltage can effectively enhance the analog and RF characteristics of TGJLFETs. The models are compared and verified with 3D TCAD simulation results.

Analytical Threshold Voltage Model of Schottky-source/drain (Schottky-S/D) double gate-all-around (DGAA) Field-Effect-Transistors (FETs)

Abstract: This paper reports an analytical model of threshold voltage for the Schottky-source/drain (Schottky-S/D) double gate-all-around (DGAA) FETs. In order to develop the threshold voltage model, the method of parabolic potential approximation is used to solve the 3-D Poisson's equation to formulate the surface potentials and threshold voltage expressions. The proposed model of threshold voltage is based on a modified definition of the threshold voltage. The influence on threshold voltage due to variation in device physical parameters like core and oxide thickness, channel thickness, and source-drain metal work function variation, and drain voltages have been investigated. The proposed analytical model results have been compared and verified against the results obtained from 3-D ATLAS device simulator from SILVACO.

Analytical Modeling of Subthreshold Current and Subthreshold Swing of Schottky-Barrier Source/Drain Double Gate-All-Around (DGAA) MOSFETs

Abstract: This paper reports analytical models of subthreshold current and subthreshold swing for the Schottky-Barrier source/drain (S/D) double gate-all-around (DGAA) MOSFETs. The subthreshold current model presented in this work is formulated by considering both thermionic transport as well as quantum-mechanical tunneling components of the current, which is dominant in the subthreshold regime of the Schottky-Barrier S/D DGAA MOSFETs operation. The proposed subthreshold current model exhibits the ambipolar behavior because of both hole and electron tunneling mechanism found in Schottky-Barrier S/D DGAA MOSFETs. The impact of variations in device physical parameter and bias conditions like channel thickness and drain voltage on the subthreshold characteristics of Schottky-Barrier S/D DGAA MOSFETs has been discussed. The results obtained from the proposed model have been validated against the results obtained from the 3-D device simulator.

Modeling of Drain Current and Analog Characteristics of Dual-Metal Quadruple Gate (DMQG) MOSFETs

Abstract: This paper presents analytical modeling and simulation of output current-voltage characteristics, output conductance, and transconductance of dual metal quadruple gate (DMQG) MOSFET. With the help of above said characteristics, this work analyzes the drain current and analog characteristics dependence on device parameters such as gate length ratio and work function ratios. The results of the modeling are compared with those obtained by a 3D ATLAS device simulator to verify the accuracy of the proposed model. Finally, it is observed that the optimum performance of a fixed channel length device is possible with higher control gate length than the screen gate length.

Energy and Area Aware Digital Fingerprint Generator Using Intrinsic Randomness

Abstract: Manufacturing variability/fluctuations is a major concern in integrated circuits and this has been exploited to design a hardware security primitive or digital fingerprint generator, referred as physical unclonable function (PUF) for resource constrained low power applications. Simulation results show that the energy consumption of proposed design is 30fJ/bit which is 6.33X lesser than [1] and it has 0.0012μm area/bit. PUFs are emerging hardware security primitive circuits widely used for secret keys generation, identification, and authentication of electronic devices. Different approaches and topologies for PUF realization have been proposed, however, main challenges associated with PUF designs include: relatively small challenge space, high resource utilization, power consumption, and susceptibility to modeling attacks. The proposed PUF is evaluated on important performance matrices of standard PUF design and it is observed that our design has extremely low resource utilization and ultra-low power consumption. Fig.1 Self-correcting overdrive voltage measurement along with amplifier stage. We propose a PUF architecture which extracts and amplifies the random fluctuations or intrinsic randomness arises during manufacturing of integrated circuits to generate secret keys. A subthreshold CMOS PUF cell is proposed as shown in Fig.1, where, transistor M1 is used to extract process fluctuations and made to operate in sub-threshold region by applying appropriate VGG and IDM1. The reason of operating M1 in sub-threshold region is that process fluctuations are dominant and the percentage variation in IDS verses VGS is higher. Also the transistors M3 and M4 of amplifier stage as shown in Fig.1 are also operated in sub-threshold region to have lower energy dissipation. The circuit draws 30nW for 1us for one bit generation thereby giving energy dissipation of 30fJ/bit. The proposed architecture employs single transistor as PUF cell, only one OPAMP and very little processing circuitry thereby making it ultra-light. The IDS of the MOSFET is related it to overdrive voltage (VGS-VT) or excess gate voltage [2]. If we allow constant VDS and IDS through M1 then, the overdrive voltage would be constant. However, random fluctuation in VT forces the VGS for self-correction to keep VGS-VT constant. In other words, random fluctuation in VT of M1 is translated to change in VGS and later amplified by the amplifier stage for secret key generation. Fig.1 sets a constant current IDM1 through M1 and the source follower ensures fixed VDS across M1. If the VT of the M1 changes then so does the source voltage thereby keeping the term (VGSVT) as constant. Since threshold voltage fluctuation is random in nature, we can say that VGS variation is random too. For array of such devices whose VTH is assumed to vary randomly due to process fluctuations and same is extracted for generation of secret keys. The extracted randomness in the form of source voltage variation in correspondence with VTH variation is further amplified by the presented amplifier stage comprising of M3 and M4. IDS in subthreshold region changes exponentially with VGS. Therefore, VS gets amplified at Vout. Node voltage ‘Vs’ corresponds to the sensed change in threshold voltage which is amplified by amplifier stage. The voltage variation at VS are such that it never goes beyond the threshold volgate of M3. This means that M3 always opearates in sub-threshold region. The length of the transistor M3 and M4 is used for gain enhancement of amplifier stage. The complete PUF architecture of secret key generation is shown in Fig.2a. This is based on the self-correcting excess voltage measurement circuit operation described in Fig 1. Challenges are applied to row and column decoders based on which a particular device is selected. Amplifier stage & Buffers Row decoder VD5 VD4 VD2 VD1 VD3 VBAIS

Effects of Lateral Spreading in 2-Dimensional Non-Uniform Doped Junctionless FinFETs

Abstract: Junctionless FETs have been extensively studied due to its remarkable feature to avoid the need of forming the ultra-steep junctions as in case of conventional transistors; however high doping concentration is required for proper operation of Junctionless FETs. In order to acquire high doping concentration using ion-implantation results in 2-D non-uniform doping profile which includes vertical as well as lateral spreading. In this work, the effect of lateral spreading of the dopants in non-uniform doped Junctionless FinFETs is analyzed through 3-D numerical simulation. The device short channel performance due to variations in the projected range (Rp), lateral straggle (ΔR t ) and dose (Q 0 ) of the implanted ions is demonstrated using Sentauras TCAD device simulator.