R
Rajiv V. Joshi
Researcher at IBM
Publications - 336
Citations - 6463
Rajiv V. Joshi is an academic researcher from IBM. The author has contributed to research in topics: Static random-access memory & CMOS. The author has an hindex of 41, co-authored 309 publications receiving 6117 citations. Previous affiliations of Rajiv V. Joshi include National University of Singapore.
Papers
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Journal ArticleDOI
Turning silicon on its edge [double gate CMOS/FinFET technology]
E.J. Nowak,Ingo Dr Aller,Thomas Ludwig,Keunwoo Kim,Rajiv V. Joshi,Ching-Te Chuang,Kerry Bernstein,Ruchir Puri +7 more
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Proceedings ArticleDOI
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events
TL;DR: A novel methodology based on an efficient form of importance sampling, mixture importance sampling is proposed for statistical SRAM design and analysis, which is comprehensive, computationally efficient and in excellent agreement with standard Monte Carlo techniques.
Patent
Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
TL;DR: In this article, a sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions.
Journal ArticleDOI
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
Terry I. Chappell,B.A. Chappell,Stanley E. Schuster,J.W. Allan,S.P. Klepner,Rajiv V. Joshi,R.L. Franch +6 more
TL;DR: In this article, the authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations.
Patent
A novel sram cell design to improve stability
TL;DR: In this paper, a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pulldown transistors and two pass-gate transistors is presented.