R
Ryan M. Mitchell
Researcher at IBM
Publications - 8
Citations - 185
Ryan M. Mitchell is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Substrate (electronics). The author has an hindex of 6, co-authored 8 publications receiving 185 citations.
Papers
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Patent
Chemical treatment to retard diffusion in a semiconductor overlayer
Kevin K. Chan,Huajie Chen,Michael A. Gribelyuk,Judson R. Holt,Woo-Hyeong Lee,Ryan M. Mitchell,Renee T. Mo,Dan Mocuta,Werner A. Rausch,Paul Ronsheim,Henry K. Utomo +10 more
TL;DR: In this article, a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa is proposed by forming a monolayer comprising carbon and oxygen between the two layers.
Proceedings ArticleDOI
Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D
Byoung Hun Lee,Anda Mocuta,Stephen W. Bedell,H. Chen,D. K. Sadana,K. Rim,P. O'Neil,R. Mo,K.K. Chan,C. Cabral,Christian Lavoie,Dan Mocuta,A. Chakravarti,Ryan M. Mitchell,J. Mezzapelle,F. Jamin,M. Sendelbach,H. Kermel,Michael A. Gribelyuk,Anthony G. Domenicucci,Keith Jenkins,Shreesh Narasimha,S.H. Ku,Meikei Ieong,I. Yang,Effendi Leobandung,Paul D. Agnello,Wilfried Haensch,Jeffrey J. Welser +28 more
TL;DR: In this article, a high quality ultra-thin TM-SGOI substrate with T/sub SOI/ < 55 nm was developed to combine the device benefits of strained silicon and SOI.
Proceedings ArticleDOI
Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow
Dae-Gyu Park,Zhijiong Luo,N. Edleman,Wenjuan Zhu,Phung T. Nguyen,Keith Kwong Hon Wong,Cyril Cabral,Paul C. Jamison,Byoung Hun Lee,Anthony I. Chou,Michael P. Chudzik,John Bruley,Oleg Gluschenkov,Paul Ronsheim,Ashima B. Chakravarti,Ryan M. Mitchell,Victor Ku,Hyungjun Kim,Elizabeth A. Duch,P. Kozlowski,Christopher P. D'Emic,Vijay Narayanan,An L. Steegen,Richard Wise,Rajarao Jammy,Rajesh Rengarajan,Hung Y. Ng,Akihisa Sekiguchi,C. Wann +28 more
TL;DR: In this article, a dual-work function metal gate with atomic layer deposition (ALD)-TaN/sub x/ for NFET and ALD-WN/sub X/ for PFET was demonstrated using a conventional CMOS process flow.
Proceedings ArticleDOI
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
J. Cai,K. Rim,A. Bryant,Keith Jenkins,C. Ouyang,D.V. Singh,Z. Ren,Kam-Leung Lee,Haizhou Yin,John M. Hergenrother,Thomas S. Kanarsky,Amit Kumar,X. Wang,S. W. Bedell,Alexander Reznicek,Harold J. Hovel,D. K. Sadana,D. Uriarte,Ryan M. Mitchell,John A. Ott,Dan Mocuta,P. O'Neil,Anda Mocuta,Effendi Leobandung,R. J. Miller,W. Haensch,Meikei Leong +26 more
TL;DR: In this paper, the scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported, indicating strain-induced enhancement can be sustained in future technology nodes.
Patent
Thin buried oxides by low-dose oxygen implantation into modified silicon
Kwang Su Sangrok-Woosung Choe,Keith E. Fogel,Siegfried L. Maurer,Ryan M. Mitchell,Devendra K. Sadana +4 more
TL;DR: In this paper, a method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided.