Proceedings ArticleDOI
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
J. Cai,K. Rim,A. Bryant,Keith Jenkins,C. Ouyang,D.V. Singh,Z. Ren,Kam-Leung Lee,Haizhou Yin,John M. Hergenrother,Thomas S. Kanarsky,Amit Kumar,X. Wang,S. W. Bedell,Alexander Reznicek,Harold J. Hovel,D. K. Sadana,D. Uriarte,Ryan M. Mitchell,John A. Ott,Dan Mocuta,P. O'Neil,Anda Mocuta,Effendi Leobandung,R. J. Miller,W. Haensch,Meikei Leong +26 more
- pp 165-168
TLDR
In this paper, the scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported, indicating strain-induced enhancement can be sustained in future technology nodes.Abstract:
The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.read more
Citations
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Journal ArticleDOI
Silicon CMOS devices beyond scaling
Wilfried Haensch,E. J. Nowak,Robert H. Dennard,Paul M. Solomon,A. Bryant,Omer H. Dokumaci,Arvind Kumar,Xinhui Wang,Jeffrey B. Johnson,Massimo V. Fischetti +9 more
TL;DR: This paper discusses device and material options to improve device performance when conventional scaling is power-constrained, separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior.
Patent
Strained-silicon cmos device and method
TL;DR: In this article, a semiconductor device and a method of forming thereof is presented, in which a uniaxial strain is produced in the device channel of the semiconductor devices.
Journal ArticleDOI
Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond
Geert Eneman,Peter Verheyen,Rita Rooyackers,F. Nouri,Lori D. Washington,R. Schreutelkamp,Victor Moroz,Louisa Smith,An De Keersgieter,M. Jurczak,Kristin De Meyer +10 more
TL;DR: In this paper, the layout dependence of Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations, and two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide.
Patent
Strained semiconductor, devices and systems and methods of formation
Leonard Forbes,Paul A. Farrar +1 more
TL;DR: In this article, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region, and the volumes of the isolation region are adjusted to provide the channel region with a desired strain.
Patent
Methods for forming a transistor and modulating channel stress
TL;DR: In this paper, methods for manufacturing transistors and altering the stress in the channel region of a single transistor are described. But the authors focus on the effect of the transistors on the channel.
References
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Journal ArticleDOI
Monte carlo analysis of electron transport in small semiconductor devices including band-structure and space-charge effects
TL;DR: In the systems considered, the inclusion of the full band structure has the effect of reducing the amount of velocity overshoot via electron transfer to upper conduction valleys, particularly at large biases and low temperatures.
Proceedings ArticleDOI
Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement
TL;DR: In this paper, a local mechanical-stress control (LMC) technique was proposed to enhance CMOS current drivability by using high mechanical stress produced by a SiN layer and Ge-ion implantation.
Proceedings ArticleDOI
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
Kern Rim,Jack O. Chu,Huajie Chen,Keith A. Jenkins,Thomas S. Kanarsky,Kam-Leung Lee,Anda Mocuta,Huilong Zhu,Ronnen Andrew Roy,J. Newbury,John A. Ott,K. Petrarca,Patricia M. Mooney,D. Lacey,Steven J. Koester,Kevin K. Chan,Diane C. Boyd,Meikei Ieong,Hon-Sum Philip Wong +18 more
TL;DR: In this article, current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFets with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/ sub eff/ below 80 nm and 60 nm.
Journal ArticleDOI
Measurement of the effect of self-heating in strained-silicon MOSFETs
Keith A. Jenkins,K. Rim +1 more
TL;DR: In this article, self-heating of strained-silicon MOSFETs is demonstrated experimentally, showing as much as 15% greater drain current for 15% Ge content than the corresponding static measurements.
Proceedings ArticleDOI
Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs
TL;DR: In this article, a novel mobility extraction technique showed that the mobility enhancements in strained Si MOSFETs were retained in deep sub-100 nm channel lengths, despite the presence of high halo doping.