Rise of silicene: A competitive 2D material

It has been demonstrated that the introduction of HfO2/ TiN gate stacks into CMOS technologies provides the means to continue with traditional device gate length scaling. However, the introduction of HfO2 as a new gate dielectric and TiN as a metallic gate electrode into the gate stack of FETs brings about new challenges for understanding reliability physics and qualification. This contribution summarizes recent advances in the understanding of charge trapping and defect generation in HfO2/ TiN gate stacks. This paper relates the electrical properties to the chemical/physical properties of the high-epsiv dielectric and discusses test procedures specifically tailored to quantify gate stack reliability of HfO2/TiN gate stacks.

Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks

This year marks a major materials milestone in the makeup of silicon-based fieldeffect transistors: in the microprocessors produced by leading manufacturers, the SiO 2 gate dielectric is being replaced by a hafnium-based dielectric. The incredible electronic properties of the SiO 2 /silicon interface are the reason that silicon has dominated the semiconductor industry and helped it grow to over $250 billion in annual sales, as reported by the Semicoriductor Industry Association (SIA), San Jose, CA. The shrinkage of transistor dimensions (Moore's law) has led to tremendous improvements in circuit speed and computer performance. At the same time, however, it has also led to exponential growth in the static power consumption of transistors due to quantum mechanical tunneling through an ever-thinner SiO 2 gate dielectric. This has spurred an intensive effort to find an alternative to SiO 2 with a higher dielectric constant (K) to temper this exploding power consumption. This article reviews the high-K materials revolution that is enabling Moore's law to continue beyond SiO 2 .

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0883769400006333

Gate Oxides Beyond SiO2

This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs) with independently switched DGs. Two types of 4T-XMOSFETs (fin and vertical) are experimentally demonstrated and their V/sub th/ controllability is thoroughly investigated in relation to the initial V/sub th/ in the DG-mode based on comprehensible modeling of the devices. Based on the investigation and simulated predictions, device design guidelines for 4T-XMOSFETs are proposed. Decreasing the workfunction of the DGs and increasing the oxide thickness of the second gate (T/sub ox2/) are preferable for improving the performance of the 4T-XMOSFET. The optimum workfunction of DGs for attaining low I/sub off(stand-by)/ and high I/sub on(active)/ under the limited V/sub g2/ condition is also proposed.

Demonstration, analysis, and device design considerations for independent DG MOSFETs

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Emerging Applications for High K Materials in VLSI Technology

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12A) for BE nFET devices to-date, consistent with simulations showing the need for ≪14A T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin Tinv (≪13A) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO/sub 2/ gate dielectrics having appropriate threshold voltages are presented for the first time.

Device design considerations for ultra-thin SOI MOSFETs

We have demonstrated aggressively scaled high performance UTSOI replacement gate CMOS featuring a HfO/sub 2//TaN gate stack which achieves T/sub inv/ of 17.5nm with greater than 100 times reduction in leakage compared to a SiON/poly-Si control sample. The atomic layer deposition process, used for the metal gate electrode material, enables the replacement gate structure to be robust at extremely small dimensions. An offset spacer together with the ultra-thin Si channel is used to demonstrate functional sub-25nm UTSOI replacement gate pFETs with high-k and metal gate for the first time. These results suggest that the replacement gate architecture is a viable option for future high performance CMOS technologies.

S. Callegari

Papers

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Device design considerations for ultra-thin SOI MOSFETs

Ultra-thin SOI replacement gate CMOS with ALD TaN/high-k gate stack