Showing papers by "Stacia Keller published in 2017"

In Situ O xide, G aN Interlayer-Based Vertical Trench MOS FET ( OG-FET ) on Bulk GaN substrates

Abstract: In this letter, we report on high breakdown voltage in situ oxide, GaN interlayer-based vertical trench MOSFETs (OG-FETs) on bulk GaN substrates. Following our previous work on OG-FETs on GaN on sapphire, utilizing a low damage gate-trench etch and using bulk GaN substrates, a breakdown voltage of 990 V with an on-resistance 2.6 $\text{m}\Omega ~\cdot $ cm2, was achieved. Without edge termination, a high breakdown field of 1.6 MV/cm was achieved in these devices.

Normally OFF Trench CAVET With Active Mg-Doped GaN as Current Blocking Layer

Abstract: A normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers. The buried Mg-doped GaN was activated using a postregrowth annealing process. The source-to-drain body diode showed an excellent p-n junction characteristics, blocking over 1 kV, sustaining a maximum blocking electric field of 3.8 MV/cm. Three-terminal breakdown voltages of trench-CAVETs, measured up to 225 V, were limited by dielectric breakdown. This paper highlights the achievement of the well-behaved buried p-n junction that has been a formidable challenge in the success of vertical GaN devices.

N-Polar GaN Cap MISHEMT With Record Power Density Exceeding 6.5 W/mm at 94 GHz

Abstract: A novel N-Polar GaN cap (MIS)high electron mobility transistor demonstrating record 6.7-W/mm power density with an associated power-added efficiency of 14.4% at 94 GHz is presented. This state-of-the-art power performance is enabled by utilizing the inherent polarization fields of N-Polar GaN in combination with a 47.5-nm in situ GaN cap layer to simultaneously mitigate dispersion and improve access region conductivity. These excellent results build upon past work through the use of optimized device dimensions and a transition from a sapphire to a substrate for reduced self-heating.

Demonstrating >1.4 kV OG-FET performance with a novel double field-plated geometry and the successful scaling of large-area devices

Abstract: A normally off (V th = 4.7 V) vertical GaN OG-FET with a 10 nm UID-GaN channel interlayer and a 50 nm in-situ Al 2 O 3 gate dielectric has been successfully demonstrated and scaled for higher current operation. By using a novel double field-plated structure for mitigating peak electric field, a high off-state breakdown voltage over 1.4 kV was achieved with a low specific on-state resistance (RON, SP) of 2.2 mΩ.cm2. The MOCVD regrown 10 nm GaN channel interlayer enabled a channel resistance lower than 10 Qmm and an average channel electron mobility of 185 cm2/Vs. The fabricated large-area transistor with a total area of 400 μm × 500 μm offered a breakdown voltage of 900 V and an on-state resistance (R on ) of 4.1 Q. Results indicate the potential of vertical GaN OG-FETs for over kV range of power electronics applications.

Dispersion Free 450-V p GaN-Gated CAVETs With Mg-ion Implanted Blocking Layer

Abstract: In this letter, a GaN-based current aperture vertical electron transistor (CAVET) with a p-type gate layer and an implantation-based current blocking structure is presented. The devices measured showed a breakdown voltage of 450 V and no dispersion. The factors limiting higher breakdown voltages in these devices were carefully studied and discussed. The devices were grown on sapphire and relied on a box-shaped Mg implanted current blocking scheme. This is the first demonstration of an implantation-based CAVET, grown on sapphire blocking of 450 V with respectable on-state characteristics.

Indium segregation in N-polar InGaN quantum wells evidenced by energy dispersive X-ray spectroscopy and atom probe tomography

Abstract: Energy dispersive X-ray spectroscopy (EDX) in scanning transmission electron microscopy and atom probe tomography are used to characterize N-polar InGaN/GaN quantum wells at the nanometer scale. Both techniques first evidence the incorporation of indium in the initial stage of the barrier layer growth and its suppression by the introduction of H2 during the growth of the barrier layer. Accumulation of indium at step edges on the vicinal N-polar surface is also observed by both techniques with an accurate quantification obtained by atom probe tomography (APT) and its 3D reconstruction ability. The use of EDX allows for a very accurate interpretation of the APT results complementing the limitations of both techniques.

First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET

Abstract: Gate dielectric plays an integral role in advancing the performance and reliability of GaN-based transistors. Si-alloying of aluminum oxide (Al2O3) dielectrics have been shown to provide a promising route to improve gate dielectric properties in GaN. In this letter, we report on the first demonstration of a GaN FET with aluminum silicon oxide (AlSiO) as the gate dielectric. Vertical normally-off GaN MOSFETs were fabricated on bulk GaN substrate. Excellent dc performance was achieved with a breakdown voltage of 1.2 kV, an ON-resistance of 2 $\text{m}\Omega $ .cm2, and a threshold voltage of 1.5 V (defined at $I_{\textsf {DS}} =1\,\,\mu \text{A}$ /mm). A high breakdown electric-field of 2.3 MV/cm was calculated in these devices. In addition to vertical GaN MOSFET results, a comparative study of Al2O3 and AlSiO-based in situ GaN MOS capacitors, including time-dependent dielectric breakdown characteristics is also presented.

Suppression of Mg propagation into subsequent layers grown by MOCVD

Abstract: Low temperature (LT) flow modulation epitaxy (FME) or “pulsed” growth was successfully used to prevent magnesium from Metalorganic Chemical Vapor Deposition (MOCVD) grown p-GaN:Mg layers riding into subsequently deposited n-type layers. Mg concentration in the subsequent layers was lowered from ∼1 × 1018 cm−3 for a medium temperature growth at 950 °C to ∼1 × 1016 cm−3 for a low temperature growth at 700 °C via FME. The slope of the Mg concentration drop in the 700 °C FME sample was 20 nm/dec—the lowest ever demonstrated by MOCVD. For growth on Mg implanted GaN layers, the drop for a medium temperature regrowth at 950 °C was ∼10 nm/dec compared to >120 nm/dec for a high temperature regrowth at 1150 °C. This drop-rate obtained at 950 °C or lower was maintained even when the growth temperature in the following layers was raised to 1150 °C. A controlled silicon doping series using LT FME was also demonstrated with the lowest and highest achieved doping levels being 5 × 1016 cm−3 and 6 × 1019 cm−3, respectively.

Metal-organic chemical vapor deposition of high quality, high indium composition N-polar InGaN layers for tunnel devices

Abstract: In this study, the growth of high quality N-polar InGaN films by metalorganic chemical vapor deposition is presented with a focus on growth process optimization for high indium compositions and the structural and tunneling properties of such films. Uniform InGaN/GaN multiple quantum well stacks with indium compositions up to 0.46 were grown with local compositional analysis performed by energy-dispersive X-ray spectroscopy within a scanning transmission electron microscope. Bright room-temperature photoluminescence up to 600 nm was observed for films with indium compositions up to 0.35. To study the tunneling behavior of the InGaN layers, N-polar GaN/In0.35Ga0.65N/GaN tunnel diodes were fabricated which reached a maximum current density of 1.7 kA/cm2 at 5 V reverse bias. Temperature-dependent measurements are presented and confirm tunneling behavior under reverse bias.

First report of scaling a normally-off in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

Abstract: GaN lateral transistors (HEMTs) continue to penetrate the power electronics market demonstrating excellent performance in the medium power applications. However, for power applications 10kW and higher, vertical GaN devices are preferred over lateral one, since the former offers higher current and power densities. To date, several different vertical transistor structures have been proposed and reported, such as in-situ oxide based vertical trench MOSFET with an undoped GaN interlayer as a channel (OGFET) [1, 2], current aperture vertical electron transistors (CAVETs) [3, 4], junction field effect transistors (JFETs) [5, 6] and MOSFETs [7, 8]. Gupta et al. have demonstrated the high performance OGFET with low specific on-state resistance (Ron, sp) recently [1]. This study presents the large device scaling of the OGFET to realize high output current.

Impact of Trench Dimensions on the Device Performance of GaN Vertical Trench MOSFETs

Abstract: In this letter, we have examined the impact of trench dimensions on the breakdown voltage and ON-resistance of trench MOSFETs fabricated on sapphire and bulk GaN substrates. Contrary to simulation studies, the breakdown voltage decreased with an increase in trench dimensions in devices fabricated on sapphire substrates. However, such breakdown voltage dependence with trench dimensions was not observed in devices fabricated on bulk GaN substrates of the same area. The observed trend on GaN on sapphire devices was associated with the equivalently reduced number of dislocations per device area. These results give an insight into how dislocations could affect breakdown voltage in power MOSFETs.

1 kV field plated in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

Abstract: In recent years, GaN trench MOSFETs have been actively investigated to achieve low on-resistance and high breakdown voltage [1-8]. The absence of a JFET region makes the trench MOSFET a favorable device structure to reduce the on-resistance. However, poor (electron) channel mobility in GaN trench MOSFETs lead to increased channel resistance. This could potentially result in reliability issues and/or high on-resistance as a large gate bias is needed to reduce the channel resistance. In our previous works, we demonstrated a novel device design (OG-FET), where enhanced channel mobility was obtained by inserting a MOCVD-regrown GaN interlayer between the trenched structure and the in-situ gate dielectric [7, 8]. The breakdown performance of OG-FETs reported in previous work was limited due to the absence of edge termination [8]. In this work, OG-FETs were fabricated with field plate based edge termination which resulted in an enhanced breakdown from 600 V (E BR ∼ 1.5 MV/cm) to 1000 V (E BR ∼ 2 MV/cm).

P–n junction diodes with polarization induced p-type graded InxGa1–xN layer

Abstract: In this study, p–n junction diodes with polarization induced p-type layer are demonstrated on Ga polar (0001) bulk GaN substrates. A quasi-p-type region is obtained by linearly grading the indium composition in un-doped InxGa1–xN layers from 0% to 5%, taking advantage of the piezoelectric and spontaneous polarization fields which exist in group III-nitride heterostructures grown in the typical (0001) or c-direction. The un-doped graded InxGa1–xN layers needed to be capped with a thin Mg-doped InxGa1–xN layer to make good ohmic contacts and to reduce the on-resistance of the p–n diodes. The Pol-p–n junction diodes exhibited similar characteristics compared to reference samples with traditional p-GaN:Mg layers. A rise in breakdown voltage from 30 to 110 V was observed when the thickness of the graded InGaN layer was increased from 100 to 600 nm at the same grade composition.

Substrates and Materials

Abstract: The choice of substrate and the material requirements for GaN-based power transistors for switching applications strongly depend on the device architecture. While to date most efforts have been directed toward the fabrication of lateral devices, vertical device layouts have recently gained interest, catalyzed by the progress in the development of larger size bulk GaN substrates. The vertical devices have the advantage that the high fields are held within the bulk of the material rather than on the surface. Large-area GaN substrates, however, are still very expensive, making a lateral device layout on a foreign substrate such as silicon, which is available in wafer sizes up to 12″, currently more attractive.

Maskless regrowth of GaN for trenched devices by MOCVD

Abstract: Blanket regrowth studies were performed on GaN trenches with varying widths and optimized for two types of devices—those that required the profile of the trench to be maintained and those that required the complete filling of trenches, i.e., a planar surface after regrowth. Low temperature Al0.22Ga0.78N growth was optimized and used as the marker layer for SEM. GaN deposition at a medium temperature of 950 °C and using N2 as carrier gas resulted primarily in growth on the (0001) plane, while the growth on the sidewalls was governed by the formation of slow growing semi-polar planes. This gave a conformal profile to the regrown GaN—useful for regrown GaN interlayer based vertical trench MOSFETs. In contrast, high temperature (1150 °C) growth in H2 resulted in high lateral growth rates. The planar surface was achieved under these conditions—a very promising result for CAVET-type devices.

N-polar GaN MIS-HEMTs on sapphire with a proposed figure of merit f max ·V DS, Q of 9.5THz.V

Abstract: GaN-based HEMTs have demonstrated outstanding performance in solid-state power amplifiers [1]. Products of f T /f max and three-terminal breakdown voltage are commonly cited to characterize the high frequency performance of power devices [2]. However, such metrics mix the results of small-signal measurements and DC breakdown measurements taken separately and therefore don't consider side effects of high voltage operation on RF performance, such as dispersion, self-heating, and material degradation. To solve this problem, a new figure of merit defined as a product of f max and its associated quiescent drain bias (V ds, q ) is proposed. Exploiting the advantages of the N-polar orientation [3] and the high film quality of MOCVD SiN x passivation layer, a 9.5 THz-V f max ·V DS, Q is achieved in this work and exceeds those of the previously reported planar MIS-HEMTs passivated by PECVD SiN x [4, 5].

Characterization of N-polar AlN in GaN/AlN/(Al,Ga)N heterostructures grown by metal-organic chemical vapor deposition

Abstract: In GaN/(Al,Ga)N high-electron-mobility transistors (HEMT), AlN interlayer between GaN channel and AlGaN barrier suppresses alloy scattering and significantly improves the electron mobility of the two-dimensional electron gas. While high concentrations of gallium were previously observed in Al-polar AlN interlayers grown by metal-organic chemical vapor deposition, the N-polar AlN (Al x Ga1?x N) films examined by atom probe tomography in this study exhibited aluminum compositions (x) equal to or higher than 95% over a wide range of growth conditions. The also investigated AlN interlayer in a N-polar GaN/AlN/AlGaN/ S.I. GaN HEMT structure possessed a similarly high x content.

Impact of oxygen precursor flow on the forward bias behavior of MOCVD-Al2O3 dielectrics grown on GaN

Abstract: This paper investigates the effects of the oxygen precursor flow supplied during metalorganic chemical vapor deposition (MOCVD) of Al2O3 films on the forward bias behavior of Al2O3/GaN metal-oxide-semiconductor capacitors. The low oxygen flow (100 sccm) delivered during the in situ growth of Al2O3 on GaN resulted in films that exhibited a stable capacitance under forward stress, a lower density of stress-generated negative fixed charges, and a higher dielectric breakdown strength compared to Al2O3 films grown under high oxygen flow (480 sccm). The low oxygen grown Al2O3 dielectrics exhibited lower gate current transients in stress/recovery measurements, providing evidence of a reduced density of trap states near the GaN conduction band and an enhanced robustness under accumulated gate stress. This work reveals oxygen flow variance in MOCVD to be a strategy for controlling the dielectric properties and performance.

A structure for increasing mobility in a high electron mobility transistor

Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of µ on InGaN thickness ( t InGaN) and indium composition ( x In) was investigated for different channel thicknesses. With optimized t InGaN and x In, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm 2 /(V•s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN / 2 nm In 0.1 Ga 0.9 N composite channel.

Vertical transport in isotype InAlN/GaN dipole induced diodes grown by molecular beam epitaxy

Abstract: InAlN dipole diodes were developed and fabricated on both (0001) Ga-Face and 000 1 ¯ N-face oriented GaN on sapphire templates by molecular beam epitaxy The orientation and direction of the InAlN polarization dipole are functions of the substrate orientation and composition, respectively Special consideration was taken to minimize growth differences and impurity uptake during growth on these orientations of opposite polarity Comparison of devices on similarly grown structures with In compositions in excess of 50% reveals that dipole diodes shows poorer forward bias performance and exhibited an increase in reverse bias leakage, regardless of orientation Similarly, (0001) Ga-face oriented InAlN at a lowered 40% In composition had poor device characteristics, namely, the absence of expected exponential turn on in forward bias By contrast, at In compositions close to 40%, 000 1 ¯ N-face oriented InAlN devices had excellent performance, with over five orders of magnitude of rectification and extracted bar

Iii-nitride transistor including a iii-n depleting layer

Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

High Spatial Resolution Energy Dispersive X-ray Spectroscopy and Atom Probe Tomography study of Indium segregation in N-polar InGaN Quantum Wells

Abstract: N-polar grown III-nitrides are very interesting materials for the fabrication of heterostructures devices such as transistors, photodetectors, solar cells or optoelectronic devices. In GaN/(In,Ga)N/GaN heterostructures with thin (In,Ga)N layers, polarization engineering allows to achieve interband tunneling. Thereby the tunneling probability is proportional to the indium concentration in the InGaN layers. Indium incorporation is higher for N-polar InGaN films than for the typically grown Ga-polar ones. N-polar III nitride films are often grown on misoriented substrates enabling the growth of smooth, high quality layers [1]. The crystal misorientation leads to the formation of surface steps, and misorientation angles of 4°-5° can result in up to 3-4 unit cell high steps. The growth of N-polar InGaN films is further complicated by the necessary reduced growth temperatures and the required absence of hydrogen in the growth ambient. In quantum well structures, however, hydrogen, which acts as surfactant and promotes the growth of smooth layers, can be introduced during GaN barrier growth, allowing the deposition of thick multiple quantum well (MQW) stacks. Ga-polar InGaN films have been extensively studied and are known for their local fluctuations in the indium composition [2]. Not much is known about the uniformity of N-polar InGaN layers.

Atom Probe Tomography Quantification of Alloy Fluctuations in (Al,In,Ga)N

Abstract: As compared with ternary nitrides systems such as InGaN, AlGaN and InAlN, quaternary (Al,In,Ga)N benefit from a significant increase in design freedom. Indeed changes in the III site atomic fraction allows for an independent choice of either band-gap, lattice constant or polarization which is particularly interesting in the field of solid state lighting, radio frequency (RF), and power electronics. Controlling the homogeneity of the alloy is of great interest to understand the physical properties of (Al,In,Ga)N based devices [1,2]. Atom probe tomography (APT) has demonstrated its ability to evidence alloy fluctuations in ternary nitride [3]. However, detection artifacts in APT could lead to misinterpretation of the actual compositions [4,5]. Calibration experiments are required to find evaporation parameters which enable for an accurate quantification of all III site atoms in (Al,In,Ga)N.

Method to achieve active p-type layer/layers in iii-nitride epitaxial or device structures having buried p-type layers

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

Abstract: In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.