H. Shang

TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.

TL;DR: A new FinFET design without S/D contact pads is proposed and a selective epitaxial process to merge individual fins is developed to address some key challenges of FINFETs for 32nm node technologies and beyond.

TL;DR: In this paper, the authors present an overview and electrical results for a novel deep trench decoupling capacitor, which can provide significant chip-level area savings, using only 1/8 silicon real estate to fabricate the same capacitance as standard planar gate oxide capacitors.

TL;DR: In this article, an aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented, where advanced stressors, thermal processes and other technology elements are integrated.

TL;DR: In this article, a bottom oxidation through STI (BOTS) was proposed to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation, achieving competitive performance with effective drive currents of I eff (N/P) = 621/453 μA/μm at I off = 10 nA/m at V DD = 0.8 V.