Showing papers by "Yogesh Singh Chauhan published in 2013"

BSIM—SPICE Models Enable FinFET and UTB IC Designs

Abstract: Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design

Abstract: We present an accurate and robust surface-potential-based compact model for simulation of circuits designed with GaN-based high-electron mobility transistors (GaN HEMTs). An accurate analytical surface-potential calculation, which we developed, is used to develop the drain and gate current model. The model is in excellent agreement with experimental data for both drain and gate current in all regions of device operation. We show the correct physical behavior and mathematical robustness of the model by performing various benchmark tests, such as DC and AC symmetry tests, reciprocity test, and harmonic balance simulations test. To the best of our knowledge, this is the first time a GaN HEMT compact model passing a range of benchmark tests has been presented.

Recent enhancements in BSIM6 bulk MOSFET model

Abstract: In this paper, we discuss the recent enhancements made in the BSIM6 bulk MOSFET model. BSIM6 is the latest compact model of bulk MOSFET from BSIM group which have body referenced charge based core. Junction capacitance model is improved over BSIM4 and is infinitely continuous around Vbs=Vbd=0V. Symmetry of the model is successfully validated by performing Gummel Symmetry Test (GST) in DC and symmetry test for capacitances in AC. Self heating model is also included in BSIM6 and test results are reported. Model capabilities are compared against an advanced 40nm CMOS technology and it is observed that simulated results are in excellent agreement with the measured data.

BSIM compact MOSFET models for SPICE simulation

Abstract: Continuous technology advancements have forced MOSFET architecture to evolve from bulk to SOI to multigate MOSFETs. BSIM compact models have helped circuit designers to realize their designs first time correct using accurate physical models used in SPICE simulation. BSIM3 and BSIM4 are threshold voltage based bulk MOSFET models while BSIM6 is charge based bulk MOSFET model, which include physical effects such as mobility degradation, current saturation, high frequency models etc. BSIM6 has been developed especially to address symmetry around Vds = 0, thus providing smooth higher order derivatives. BSIM-CMG is a CMC standard surface potential based model for common symmetric double, triple, quadruple and surround gate (nanowire) MOSFETs. Long channel DIBL also called Drain-Induced Threshold Shift (DITS) effect and asymmetric charge weighing factor etc. have been recently included in it. BSIM-IMG is a surface potential based model to simulate ultra-thin body devices such as UTBSOI but also other thin body devices such as MOS2 transistor.

High voltage LDMOSFET modeling using BSIM6 as intrinsic-MOS model

Abstract: Here, we report high voltage MOSFET modeling using BSIM6 model. The model has two components - intrinsic MOSFET channel of LDMOS modeled by BSIM6 and a drift region modeled by non-linear drift resistance. BSIM6 is the next generation bulk MOSFET model in BSIM family of models. It also have the model of Self Heating Effect (SHE) which is very important for high power devices like LDMOS. This model shows good behaviour over wide range of gate and drain bias conditions including convergence. Some of the effects like Quasi-saturation, self-heating and impact ionization are modelled by the combination of BSIM6 and drift-resistance models. We have validated this model on the simulated characteristics generated by TCAD and then, on the measured characteristics of a LDMOS device, where it shows excellent accuracy over entire bias range.

A surface potential based model for GaN HEMTs

Abstract: In this work a surface potential based compact model is presented for GaN material based High Electron Mobility Transistors We have developed model for charges, drain current and gd (output conductance) which is surface potential based and physically accurate Our model has shown excellent agreement with experimental data for drain current and gd This model is capable of showing correct physical behavior and is robust which can be observed through various benchmark tests, such as AC symmetry test, DC symmetry test and self-heating test We have used Agilent ICCAP, ADS and Synopsys Hspice for our simulations

Modeling and Simulation Methodology for SOA-Aware Circuit Design in DC and Pulsed-Mode Operation of HV MOSFETs

Abstract: In this paper, we present a modeling and simulation methodology for safe-operating-area (SOA)-aware circuit design in dc and pulsed-mode operation of high-voltage MOSFETs (HV MOSFETs). The developed methodology gives an accurate description of the SOA of devices under dc and, more importantly, transient inputs, taking into account the width and duty-cycle of the pulse. To the best of the authors' knowledge, this is the first time such a methodology integrated with circuit design tools is presented. It is shown through simulation of standard circuits of HV MOSFETs that the proposed methodology avoids overdesigns and enables circuit designers to use the high-voltage technology to its full potential.