Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2020"

Link Performance Comparison based on Insertion Loss: NRZ, PAM3, PAM4, and ENRZ

Abstract: This work presents a comparative study, analyzing performance of NRZ (Non-Return-to-Zero), PAM4 (Pulse Amplitude Modulation of 4-level), PAM3, and ENRZ (Ensemble NRZ) in terms of sensitivity to channel loss. The advantageous of each signaling scheme based on residual eye opening are being discussed.

Policy Gradient Reinforcement Learning-based Optimal Decoupling Capacitor Design Method for 2.5-D/3-D ICs using Transformer Network

Abstract: In this paper, we first propose a policy gradient reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for 2.5-D/3-D integrated circuits (ICs) using a transformer network. The proposed method can provide an optimal decap design that meets target impedance. Unlike previous value-based RL methods with simple value approximators such as multi-layer perceptron (MLP) and convolutional neural network (CNN), the proposed method directly parameterizes policy using an attention-based transformer network model. The model is trained through the policy gradient algorithm so that it can achieve larger action space, i.e. search space. For verification, we applied the proposed method to a test hierarchical power distribution network (PDN). We compared convergence results depending on the action space with the previous value-based RL method. As a result, it is validated that the proposed method can cover ×4 times larger action space than that of the previous work.

Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk

Abstract: In this paper, we propose the through silicon via (TSV) array design optimization method using deep reinforcement learning (DRL) framework. The agent trained through the proposed method can provide an optimal TSV array that minimizes far-end crosstalk (FEXT) in one single step. We define the state, action, and reward that are elements of the Markov Decision Process (MDP) for optimizing the TSV array considering FEXT and train a deep q network (DQN) agent. For verification, we applied the proposed method to a 3 by 3 through silicon via array at stacked DRAM of High Bandwidth Memory (HBM). The network converged well, and as the result, the proposed method provided the optimal design that satisfies the target FEXT in which 3 dB lower than the initial design.

Invertible Neural Networks for Inverse Design of CTLE in High-speed Channels

Abstract: Designing CTLE of high-speed channels can be complicated and time consuming. To alleviate this issue, this paper investigates the invertible neural networks (INNs) for inverse design of the CTLE. In this approach, a desired eye height and eye width is given, and the algorithm finds the corresponding peaking frequency and gain value of the CTLE. INN is a special type of neural networks that can be traversed in both forward and reverse directions. An advantage of this network is producing distribution of the input variables based on the desired output. This feature enables the algorithm to provide multiple solutions when a multi-modal distribution is produced. Thus, the user can choose the appropriate solution based on other constraints. A numerical example for inverse design of CTLE of a SerDes channel is provided, which results in moderate accuracy. However, other variations of the example show that the accuracy is case dependent which implies improvements on the algorithm is needed.

Fast Power Integrity Analysis of PDNs with Arbitrarily Shaped Power-Ground Plane Pairs

Abstract: A Newton-Raphson (N-R) based method is developed for performance evaluation of power delivery networks (PDN) with arbitrarily shaped parallel-plate power/ground plane pairs. The proposed method allows for PI assessment in a few iteration steps while providing significant computational efficiency compared to alternative methods. The proposed method is tested on a practical example and the results are observed in good agreement with those obtained from a numerical electromagnetic (EM) simulator.

Temperature and Dielectric Surface Roughness dependent Performance Analysis of Cu-Graphene Hybrid Interconnects

Abstract: To exploit the superior performance of copper and graphene interconnects, hybrid interconnects are seen as a promising interconnect technology for future technology nodes. Dielectric surface roughness is a process induced phenomenon that affects the performance of the interconnects. This paper presents an in-depth investigation on the impact of temperature and dielectric surface roughness on performance parameters of Cu-Graphene hybrid interconnects.

Gaussian Process surrogate model for variability analysis of RF circuits

Abstract: Non-intrusive methods for studying processes involving variables changing such as design optimization, manufacture variation etc. require evaluations of the quantity of interests for a numerous times. These methods, hence, rely on an accurate surrogate model of the process under study. Gaussian Process (GP) is a well-known non-parametric modeling technique for surrogate modeling. This paper explores the effectiveness of GP to model RF applications. The analysis of a milimeter-wave bandpass filter is presented to illustrate the method.

Signal Integrity Analysis of Automotive CAN-FD Networks with Series Damping Resistor-Equipped Joint Connectors

Abstract: In this paper, for the first time, we propose a noise suppression scheme for automotive controller area networks with flexible data rate (CAN-FD) networks that is using series damping resistor-equipped joint connectors (JCs). A CAN-FD is a bus protocol that allows multiple electrical control units (ECUs) to cross-communicate. Signal reflections at the numerous nodes and branches propagate across the entire network and considerably reduce the signal integrity of the communication. The resistors installed in series with signal pins of JCs can attenuate the signal reflection at the expense of DC power loss. We extracted S-parameter models of interconnects of a CAN-FD network, i.e., twisted pair cables, JCs, and configured them with ECU circuit models. We ran time-domain simulations, and evaluated the performance of the JCs by observing the eye diagrams between the ECUs. By equipping optimal size of resistors, the JCs could improve the width of the eye diagrams compared to the JCs without series damping resistors with an expense of DC margin.

A Hexa-band Gysel Power Divider for Microwave Applications

Abstract: This paper presents a hexa-band Gysel power divider (GPD) for microwave applications. By replacing each ʎ/4 transmission line (TL) of the conventional GPD by the hexa-band ʎ/4 TL the proposed GPD has been developed. In order to verify the approach, a hexa-band GPD has been developed on Printed Circuit Board (PCB) for f 1 = Long Term Evolution (LTE) 0.7GHz, f 2 = LTE1.7GHz, f 3 = LTE2.6GHz, f 4 = 3.9GHz, f 5 = Public Safety Band 4.9GHz and f 6 = Wireless Local Area Network (WLAN) 5.8GHz wireless applications and tested. Return loss and isolation better than 13dB has been obtained while preserving the transmission 3.5dB for all the six bands. The first time a hexa-band GPD has been developed.

Design and Analysis of Thermal Transmission Line based Embedded Cooling Structures for High Bandwidth Memory Module and 2.5D/3D ICs

Abstract: In this paper, we firstly proposed a thermal transmission line (TTL) based embedded cooling structure for advanced thermal management of a next-generation high bandwidth memory (HBM) module. Thermal issues are critical to the development of HBM and 2.5D/3D ICs. The proposed TTL based embedded cooling structures can be one of the promising thermal management solutions for the 2.5D/3D ICs. The previous embedded cooling structures have thermal management limitations of the difficulties of cooling the internal heat of the 2.5D/3D ICs each layer. The proposed TTL transfers internal heat to the coolant to lowering junction temperature. Moreover, we checked the fabrication feasibility of the TTL with through silicon vias (TSVs). By using 3D electromagnetic (EM) and 3D fluent simulations, we analyzed the proposed TTL considering signal integrity (SI) and thermal integrity (TI). SI analysis showed the TTL does not contribute critical SI issues for HBM on-chip TSV channels. TI analysis provided the thermal management superiority of the TTL. As a result, it showed the improvement of TI of HBM module decreased HBM junction temperature by 4.789°C compared to the previous embedded cooling structure.

Multiphysics challenges with Heterogeneous Integrated Voltage Regulator based Power Delivery Architectures

Abstract: Heterogeneous integration of power delivery circuits provides for a system-scaling opportunity in the post-Moore era. However, the integrated voltage regulator (IVR) poses complex design challenges. In this paper, the fundamental challenges and benefits, arising from the IVR-based power delivery system, in the electrical, thermal, and electromagnetics domains are analyzed. To verify the analysis, a comparison study of the regulator architectures with and without heterogeneous integration is considered. Also, metrics for the IVR design space are provided as measures to address its integration complexity and figure-of-merit.

Performances of a Low Power Latch due to PSN

Abstract: This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.

Power Distribution Network Optimization for On-Die Regulator with Laplace Transform Technique

Abstract: This paper introduces a methodology to co-design on-chip linear dropout regulator (LDO) with power distribution network of package and PCB board based on Laplace transform method. A practical methodology demonstrates the effectiveness and the efficiency of the Laplace model in the time domain and is derived that takes into account LDO-PDN system impedance response. LDO pass transistor size and output decoupling capacitor optimization flow is proposed to meet the system voltage noise requirements. The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.

Iterative Loewner Matrix Passivity Correction Technique

Abstract: This paper presents a passive correction technique using the Loewner matrix (LM) algorithm for modeling distributed circuits characterized by frequency-domain data. A methodology is described based on a frequency point selection technique, which increases the likelihood that the reduced Loewner matrices form a passive system. This process of adding data points to correct passivity is repeated until the LM model is passive. A numerical example is provided to illustrate the validity of the proposed work.

A Miniaturized and High Frequency Response 35GHz FMCW Radar for Short Range Target Detections

Abstract: A miniaturized and high frequency response 35 GHz frequency modulated continuous wave (FMCW) radar system is presented for short range target detections. The system mainly consists of two antennas, a single chip transceiver and a signal processor. Thanks to our design and integrated techniques, high performance of the system is achieved and also verified by experimental results using our fabricated prototype. Our results show that the detection accuracy of 0.2m can be achieved for 15cm *15cm metal targets within detection distance of 12m, along with the radar system total size of 29mm in diameter, which agrees well with our design.

Deep Reinforcement Learning-based Interconnection Design for 3D X-Point Array Structure Considering Signal Integrity

Abstract: In this paper, we, for the first time, proposed the Reinforcement Learning (RL) based interconnection design for 3D X-Point array structure considering crosstalk and IR drop. We applied the Markov Decision Process (MDP) to correspond to finding the optimal interconnection design problem to RL problem. We defined interconnection state to the vector, design to the action and the number of bits, crosstalk and IR drop are considered as the reward. The Proximal Policy Optimization (PPO) and Long Short-Term Memory (LSTM) are used to RL algorithms. The proposed interconnection design model is well trained and shows convergence of reward score in 16×16, 32×32 and 64×64 cases. We verified that the trained model finds out optimal interconnection design considering both memory size and signal integrity issues.

SAR ADC with Optical Frontend for Biosensor Applications

Abstract: This article introduces a 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with analog front-end and optical front-end circuit to detect biomedical signal for electroencephalography (EEG) applications. The proposed integrated design is 16-bit SAR ADC that achieves exceptional performance while consuming very low consumption and high dynamic range (DR) in parallel two pairs of 8-bit SAR ADC with SC low-pass filter. The dynamic comparator contains an asynchronous control sampling switches between high and low potential to internally proposed the timing source to optimizing dissipation of half comparator and digital circuit. The average switching energy and total capacitance are reduced.

Investigation of Sideway Coupling Effects of Virtual Ground in Three Types of Coupled Line with Mixed-mode Stimuli

Abstract: Some suggested that four-port single-ended scattering S-parameters (simulated or measured) be converted and used to represent mixed-mode S-parameters; the approach we label here as "SE-matrix converted," or simply "SE-conv." SE-conv is often preferred, since the mixed-mode signal sources and probes are not readily or easily available. To employ the SE-conv formulation, the two lines have to be loosely coupled. This restriction curtails in differential bias in the mixed-mode feeding the considerations of 1) existence of virtual ground, and 2) defect ground that may be present in the system ground. First, when the virtual ground existing between lines is not considered (due to loosely coupling assumption), detailed capacitive referencing (line held at +V to virtual ground, and virtual ground to other line held at –V in differential feed) is thus ignored. Three CPL configurations were employed here to investigate the impacts of close coupling, including the effect of virtual ground and its associated capacitive referencing. The progress is reported in this paper. Secondly, effects of ground defect is directly picked up by SE feeding, while in mixed-mode feeding, the effect is somehow reduced (or resisted) by the virtual ground. The investigation on this issue is in progress, and we will report the results later. Keywords— CPL (Coupled Line), Single-ended and mixed-mode feeds, Differential & common mode stimuli, Coupled line, Stripline, Microstrip, and Co-planar ground, Virtual ground, Defect ground, Scattering parameters, Network analyzer

A Large-Signal Method for Modeling Vccin feedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators

Abstract: A simple and accurate method is proposed to model the Vccin feedthrough noise in microprocessors with Fully Integrated Voltage Regulators (FIVR). The method is based on averaged state-space models of FIVR and the Vccin network derived from the pole-residue models.

An Improved Method of Finding Complex Permittivity of Lossy Liquids

Abstract: An improved transmission/reflection method for high DK, DF liquid material is proposed. The conventional T/R method often requires a nearly-matched transmission line feeding, which is difficult to realize in high DK liquids. To overcome this problem, in this paper we propose a reference impedance transform technique based on the concept of pseudo-wave. The transformed S parameters will then exhibit better transmission due to better (virtual) matching. In addition, a time-gating method is proposed to solve the resulting equations and obtain smoother complex permittivity w.r.t. frequency. Experiments are conducted to verify the proposed method.

On Die SSN Methodology for High Speed IO

Abstract: In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.

On Die Clock Tree PSIJ Simplified

Abstract: A simplified methodology for On-Die clock tree Power Supply Induced Jitter (PSIJ) analysis is put forth. The approach estimates jitter induced on a clock output (CK) without introducing significant error while significantly reducing simulation times. Approach relies on analysis of various transfer functions of on-die linear regulators. The accuracy of this simplified approach is highly dependent on on-die linear regulator design.

Application of Different Learning Methods for the Modelling of Microstrip Characteristics

Abstract: In this paper, the performance of four machine learning regressions like Support Vector Machine (SVM), Least Square-Support Vector Machine (LS-SVM), Gaussian Process Regression (GPR) and Random Forest method (RF) are investigated by means of an illustrative example referring to the characteristic impedance of a microstrip line in terms of electrical and geometrical parameters. The required dataset for training is obtained from a set of parametric electromagnetic simulations. The performance comparison of the four methods is done in the presence and absence of numerical noise and inaccuracies affecting the training samples. The results of our comparison provide a guidance for the proper method selection to model the electromagnetic characteristics of interconnects for high-speed signals: advantages and drawbacks of each of the proposed techniques clearly emerge from this analysis.

A New High Performance Miniaturization Antenna for VHF/UHF/GPS Maritime Application

Abstract: A new high performance maritime rescue antenna is presented, including VHF, UHF and GPS bands in buoy miniaturization environment. By using innovative method of coaxial design, each of their desired radiation pattern and return loss are achieved. Specially, two VHF antennas, with 10dB impedance bandwidth of 4% (155-162MHz) and 8% (230-250MHz) respectively, port isolation of 15dBi are carefully designed. Meanwhile, the gain of VHF antennas is greater than 2dBi in elevation plane and the variation less than 1dBi in azimuthal plane. Circularly polarized UHF antenna achieves the wide beamwidth of 120 degrees at 406MHz, under the gain of 4.5dBi in elevation plane and axis ratio less than 3dBi with quadrifilar spiral inverted-F structure and shorted stub. GPS antenna is in the form of microstrip patch, which has good radiation characteristics. All antennas are finally verified by both simulations and measurements, showing their great potential applications in maritime rescue system.

Communication Distance Enhancement of Transmission Line Coupler by Using Parallelized Driver ICs

Abstract: Non-contact communication can be realized by using a transmission line coupler. A highly durable system can be created by using contactless communication. The transmission line coupler has a trade-off relationship between long-distance transmission and compact packaging, which is an implementation issue. In this paper, we have developed a system that doubles the transmission power by parallelizing the driver ICs and achieves both compact packaging and communication distance enhancement.

Effective Segmentation approach of Package-to-PCB modeling using Full-Wave EM field Solver

Abstract: Today’s design of high data rate (25 Gbps+) channel calls out modeling of the package to printed circuit board interface using full-wave electromagnetic field solvers. The interaction of the package ball grid array and printed circuit board pad along with via to trace routing leads to an impedance discontinuity, which needs to be modeled given sensitivity of channel performance to reflections at high data rates. There is a need to break the package-to-PCB full model into segments as the use of full-wave electromagnetic field solvers are limited by available computational resources & simulation time. This work explores the package to printed circuit board modeling using full-wave electromagnetic field solver through the segmentation approach. Presented are results on placement of reference planes at different locations in creating segments and then cascading using S-parameters. Results through insertion loss, return loss, crosstalk and time domain reflectometry are shown in comparing the results of the segmentation approach with that of the full model using electromagnetic field solver. This effort is an attempt at presenting a valid approach at placement of reference planes through the segmentation approach using full-wave electromagnetic field solver for high speed package-to-PCB modeling.

NEXT & FEXT Prediction using Hybrid 2D-3D Solver for Fast Electromagnetic Analysis

Abstract: The excessive time and memory requirement for a 3D full-wave solver is a challenge in simulation for signal integrity. This paper presents a hybrid 2D-3D electromagnetic full-wave simulator based on automated segmentation of layout. The novelty of this work is primarily in the classification of segments of layout as 2D or 3D segments using corner points and analysis of the electric field profile. An appropriate error metric is defined and is used in the process of this classification. Finally, cascading studies are performed using different port-structures for concatenating segments to get the overall response. Numerical results for a differential pair is presented with near-end crosstalk (NEXT) and far-end crosstalk (FEXT) to illustrate the time versus accuracy merits.

Deep Neural Network-based Lumped Circuit Modeling using Impedance Curve

Abstract: Usually, modeling takes a long time because it depends on the engineer's experience and is done through repetitive tuning. In this paper, we propose a deep neural network (DNN)-based lumped circuit modeling method using an impedance curve. The proposed method provides a fast and accurate electrical circuit model of inductance (L), capacitance (C), and conductance (G) using a DNN. Since the LCG parameters are predicted by the impedance curve, it is flexible for various applications. For accurately predicting lumped circuit parameters, the DNN model is designed and trained through various case studies. As a result, the proposed method predicts 100% accuracy in inductance and conductance, and 92% accuracy in capacitance. In other words, the proposed method successfully models the electrical characteristics of various applications.

Divide by Two Injection-Locked Frequency Divider Using 3-D Inductive Mutual-Coupling

Abstract: The article designs a high-performance wide-band injection locked frequency divider by 2 (ILFD ÷2) from tsmc 0.18 μm CMOS technology. The ILFD proposes 3-D transformer-coupled resonator with two resonant frequencies. The ILFD can operate in three modes with overlapped locking ranges. The optimal bias condition yields wide locking range during low power with high figure of merit. The locking range is 3.3 GHz at 1.83 mW from 2.3 to 5.6 GHz.

Design and Measurement of a HDMI 2.1 Connector for 8K TV considering Signal Integrity

Abstract: In this paper, we propose the design of a HDMI 2.1 connector for 8K TV considering signal integrity (SI). Also, we firstly measure the proposed HDMI 2.1 connector. To achieve the high data rate, connector should be designed by considering not only mechanical characteristics but also electrical characteristics. We design the HDMI 2.1 connector considering SI including characteristic impedance, differential insertion loss and attenuation to crosstalk ratio (ACR). We revise the structure of metal pins and dielectric materials for improving the SI performances. Proposed HDMI 2.1 connector was verified by time-domain and frequency domain simulation using the 3D electromagnetic (EM) simulator. Proposed HDMI 2.1 connector showed improve SI performance than previous connector. Also, proposed connector was verified through measurement. With the proposed HDMI design, it shows better SI characteristics at the 24 Gbps which is expected to next generation HDMI connector’s data rate.