Showing papers in "IEEE Transactions on Device and Materials Reliability in 2001"

Soft errors in advanced semiconductor devices-part I: the three radiation sources

Abstract: In this review paper, we summarize the key distinguishing characteristics and sources of the three primary radiation mechanisms responsible for inducing soft errors in semiconductor devices and discuss methods useful for reducing the impact of the effects in final packaged parts.

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Abstract: The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 mm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown, Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

Relation between breakdown mode and location in short-channel nMOSFETs and its impact on reliability specifications

Abstract: A method to determine the breakdown position in short channel nMOSFETs is introduced. We find that soft breakdown occurs exclusively in the transistor channel, while the hardest circuit-killing breakdowns occur above the source and drain extension regions. Since these breakdowns make up only a small fraction of all breakdowns, a relaxation of the reliability specification is possible.

Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices

Abstract: The gate-driven effect and substrate-triggered effect on electrostatic discharge (ESD) robustness of CMOS devices are measured and compared in this paper. The operation principles of gate-grounded design, gate-driven design, and substrate-triggered design on CMOS devices for ESD protection are explained clearly by energy-band diagrams. The relations between ESD robustness and the devices with different triggered methods are also explained by transmission line pulsing (TLP) measured results and energy-band diagrams. The turn-on mechanisms of nMOS devices with triggered methods are further verified using the emission microscope (EMMI) photographs of the nMOS devices under current stress. The experimental results confirm that the substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices better than the gate-driven design. The human body model (HBM) ESD level of nMOS with a W/L of 400 /spl mu/m/0.8 /spl mu/m in a silicided CMOS process can be improved from the original 3.5 kV to over 8 kV by using the substrate-triggered design. The gate-driven design cannot continually improve the ESD level of the device in the same deep-submicron CMOS process.

Role of E-E scattering in the enhancement of channel hot carrier degradation of deep-submicron NMOSFETs at high V/sub GS/ conditions

Abstract: It has been reported in the literature that in deep-submicron nMOSFETs, the worst channel hot carrier (CHC) degradation is not near the peak substrate current (as predicted by the lucky electron model), but at the V/sub GS/=V/sub DS/ bias condition. We propose a new CHC model based on an electron-electron scattering-induced hot carrier (HC) mechanism, that explains the worsening of the HC damage at high VGs and agrees well with the HC lifetime measured over the moderate to high gate voltage range and a wide L/sub EFF/ range. The predicted quadratic source current dependence of HC lifetime at mid V/sub GS//V/sub DS/, evolving into a cubic dependence at high V/sub GS//V/sub DS/, matches well the observed behavior.

Electromigration modeling for integrated circuit interconnect reliability analysis

Abstract: A simple one-dimensional continuum model for electromigration transport has been fairly successful as a tool for understanding many empirical observations of electromigration phenomena in encapsulated interconnect lines on integrated circuits. In this paper, the development of the one-dimensional continuum electromigration model is reviewed, Comparisons are made with previous models, emphasizing the important similarities and differences,.

Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?

Abstract: In this paper, the phenomenon of channel hot carrier (CHC) induced degradation in transistors and its relation to ESD reliability is reviewed. The principles of CHC and the tradeoff with ESD during technology development from channel/drain engineering, including consideration for mixed voltage designs, are discussed. Also, latent damage due to ESD-induced effects on CHC is considered. Finally, it is shown how the generation of hot carriers can help in the optimization of the performance of advanced ESD protection concepts.

Conductive materials for ESD applications: an overview

Abstract: Polymer resins, because of their low cost, versatility, and ease of use, are the principal component in many static-control items. These items include containers and packages used to store and transport sensitive electronics. This paper seeks to explain how polymers are used for these demanding applications by providing a basic tutorial in polymer science as well as a brief description of the commercial polymers used in static-control products. This paper also contains a review of the various ways of imparting electrical conductivity on plastic resins through the use of antistatic agents, conductive fillers, and intrinsically conductive polymers.

Stress-induced leakage current (SILC) and oxide breakdown: are they from the same oxide traps?

Abstract: Many research groups have used stress-induced leakage current SILC as a mean to measure the oxide traps (defects) buildup in the oxide film during electrical stress. It is commonly believed that these very same traps will lead to oxide breakdown when their density reaches a critical value. We studied the annealing kinetic of SILC as well as, the oxide breakdown distribution and found that they are quite different. Our result casts serious doubt on the validity of the popular assumption.

New global insight in ultrathin oxide reliability using accurate experimental methodology and comprehensive database

Abstract: In this paper, we critically examine several important experimental aspects concerning ultrathin oxide reliability. The statistical nature of breakdown measurements and the impact on data interpretation is discussed. Thickness dependence of Weibull slopes and its impact on reliability projection is reviewed. We also investigate the voltage-dependent voltage acceleration using two independent experimental methods over a wide range of oxide thickness values. Within the framework of a general defect generation model, we explore the possibility of a voltage-dependent defect generation rate to account for the increase in voltage acceleration with decreasing voltages. Using direct experimental results, we clarify that strong temperature dependence found on ultrathin oxides is a voltage effect, not a thickness effect as previously suggested, In the context of voltage-dependent voltage acceleration, we experimentally resolve various seemingly contradicting and confusing observations such as temperature-independent voltage acceleration and non-Arrhenius temperature dependence found on ultrathin oxides. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domain constructed from two important empirical principles based on comprehensive experimental database.

Accurate wafer-level measurement of ESD protection device turn-on using a modified very fast transmission-line pulse system

Abstract: Quantifying the turn-on behavior of electrostatic discharge (ESD) protection devices under subnanosecond transients is critical to achieving robust protection against the Charged Device Model stress. A wafer-level very fast transmission-line pulse system (VFTLP) has been developed and is shown to successfully measure the turn-on time of a common ESD protection device. Both formal analysis and practical details regarding VFTLP system construction and operation are documented.

Mobile ion-induced data retention failure in NOR flash memory cell

Abstract: Data retention failures due to nonoptimized processes in NOR-type flash memory cells are presented. Contrary to the charge leakage through defective oxide dielectric surrounding the floating gate, the data loss observed depends on whether the bit line contact is close to the cell or not. It is found that the data loss exhibits a charge-state dependence during baking stresses as well as temperature dependence. Based on experimental results, sodium movement in sidewall spacers is established as an origin for the data retention failure in NOR-type flash memory cells. Employing a thin nitride overlayer results in a good data retention, supporting the hypothesis of sodium movement.

Comparison of soft-breakdown triggers for large-area capacitors under constant voltage stress

Abstract: This work quantitatively compares soft breakdown identification methods for constant voltage stress of large-area nMOS capacitors (up to 10 mm/sup 2/) with 1.8- to 12-nm gate-oxide thickness (with negative gate voltage). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation. We present a method to quantify the system background noise, and show results of data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.

Accurate and robust noise-based trigger algorithm for soft breakdown detection in ultrathin gate dielectrics

Abstract: Oxide breakdown is one of the most threatening failure mechanisms in integrated circuits. As the oxide thickness is decreased in the sub-5-nm range, the breakdown definition, itself is no longer clear and its detection becomes problematic. A new algorithm for accurate and robust automatic triggering on soft breakdown (SBD) during constant voltage stress based on gate current noise increase is presented. Triggering on current spikes or pre-BD events is avoided. This test assures correct automatic SBD detection in a wide range of stress conditions and various geometries, with an execution speed that provides acceptable time resolution.

Effect of a thin ionized-metal-plasma deposited Cu layer on the properties and thermal stability of Cu-TaN-SiO/sub 2/-Si structures

Abstract: Cu-TaN-SiO/sub 2/-Si structures, fabricated in a three-in-one system, were systematically investigated using various techniques. By depositing a thin plasma-metal-plasma (IMP) Cu layer on the TaN barrier prior to the copper film deposited using metal-organic chemical vapor deposition, the sheet resistance, uniformity, and adhesion of the metal in the Cu-TaN-SiO/sub 2/-Si structures can be significantly improved. The thermal stability of the structures can also be enhanced due to the reduction of Cu diffusion and out-diffusion of Si, Ta, and O elements. These observations are of great value for application of chemical vapor deposition Cu-IMP Cu in multilevel interconnects of deep-submicron integrated circuits.

Effects of device design on InP-based HBT thermal resistance

Abstract: The thermal resistance of InP-based single and double heterojunction bipolar transistors has been measured. The double heterojunction bipolar transistor (DHBT) device employs an InP collector to improve thermal conductivity and reduce the base-emitter junction temperature rise. DHBTs were grown with heavily doped InGaAs or InP sub-collectors for low resistance contacts. As expected, the all-InP collector (sub-collector and collector) had the lowest thermal resistance while the all-InGaAs collector (sub-collector and collector) had the highest thermal resistance. For a device with emitter size of 1 /spl times/ 3 /spl mu/m/sup 2/, the room temperature thermal resistance of the all-InP collector DHBT was 3.9/spl deg/C/mW. The DHBT with an InGaAs sub-collector had a thermal resistance of 5.6/spl deg/C/mW, while the SHBT had a thermal resistance of 12.3/spl deg/C/mW. Also compared were effects of device layout parameters on thermal resistance and the effect of the topside metal thickness. Devices with the largest perimeter-to-area ratio had the lowest thermal resistance when normalized to emitter area. HBTs with conservative alignment tolerances (L1) had similar thermal resistance to those with aggressive alignment tolerances (L2). The reduced parasitic capacitance of the L2-style SHBT improved the device f/sub T/ from 150 to 183 GHz at 6.0-mA collector current. Alternately, the reduced parasitics allowed the SHBT to operate at 150 GHz f/sub T/ at 2.9 mA, reducing the junction temperature rise by more than half. Doubling the topside metal thickness improved the thermal resistance by 31% at room temperature.

Hot carrier effects in Si-SiGe HBTs

Abstract: Life tests were performed at room temperature on Si-SiGe HBTs by reverse biasing the base-emitter junction under open collector conditions. The effects on the DC, the low-frequency noise, and the microwave characteristics were investigated both by the analysis of experimental data and by simulations and analytical models. The stress-induced surface damage close to the emitter perimeter was identified to be the degradation mechanism mainly responsible for the variations observed, in all the investigated parameters.

Junction leakage current degradation under the off-state bias-temperature stress: a new reliability assessment method for high-density DRAMs

Abstract: A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed.

Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET

Abstract: A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si/sub 3/N/sub 4/ gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As a result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si/sub 3/N/sub 4/ gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability.

Quantifying the nature of hot carrier degradation in the spacer region of LDD nMOSFETs

Abstract: A detailed quantitative analysis of the hot carrier degradation in the spacer region of LDD nMOSFETs using stress conditions for maximum hole (V/sub g/ /spl sim/ V/sub t/), substrate (I/sub submax/) and electron (V/sub g/ = V/sub d/) current from microseconds is presented. Damage in the spacer region reveals a two-stage drain series resistance degradation with an early stage lasting about 100 ms. The nature of damage is investigated by alternate electron, hole injection, and charge pumping measurements. It is seen that the hot carrier damage in the spacer oxide in the early stage is dominated by interface state creation with no evidence of significant damage by trapping mechanism either by electrons or holes. These results are in contrast to degradation behavior in the channel region where damage by trapping is a well-established mechanism of degradation under electron or hole injection.

Depassivation of latent plasma damage in nMOSFETs

Abstract: Indispensable in CMOS manufacturing, plasma treatments may result in a latent damage in gate oxides. We propose a method to detect this latent damage as a function of the area of the multifingered metal pad connected to the gate, by using an experimental method based on constant current stress and oxide trapped charge measurements. We measured a power law behavior describing the dependence of the trapped charge on the injected charge.

Reliability monitoring and screening issues with ultrathin gate dielectric devices

Abstract: Installing appropriate quality and reliability monitoring procedures for ultrathin gate dielectrics is of utmost importance. Ensuring the integrity of VLSI products and unwavering customer satisfaction are the top priorities. Several key strategic avenues have been pursued to accomplish those priorities. First, basic tool and processing monitoring and measurement procedures are put into place for categories such as metallic contamination, foreign material control, and semiconductor stress-induced defects such as dislocations and stacking faults. Second, a new voltage ramp breakdown test, especially designed for ultrathin gate dielectrics, is installed based on a one-to-one correlation with TDDB testing, from which a fail criterion for minimum required breakdown voltage of the distribution is defined. The voltage ramp test is capable of identifying weaknesses or failures for either the intrinsic or extrinsic parts of the failure rate distribution. The voltage ramp test is installed at various processing levels starting with post silicide probing (PSP) utilizing very large guide area/perimeter structures (area>0.5 mm/sup 2//chip, and perimeter >1 meter/chip) with both shallow trench isolation (STI) and diffusion perimeters. Third, a voltage breakdown test is put into place for in-line charging effects at various processing levels. The structure used employs minimum polysilicon linewidth devices and contains a nonantenna reference device as well as a variety of antenna structures for various design levels starting with polysilicon and including all via, contact, and metal levels. Such a dielectric breakdown test for charging is also well correlated with other device failure mechanisms such as hot carriers. Fourth, a new methodology was adopted based on a one-to-one quantitative correlation between lifetime as derived from accelerated TDDB testing and the initial value of gate dielectric leakage at a predetermined value(s) of voltage(s). This excellent correlation was verified for gate dielectric thickness ranging from 10 nm to below 3 nm. Fifth, at product level, the standby I/sub ddQ/ and I/sub dd/ currents are measured and tracked for changes under accelerated stress conditions for numerous scan chains. This measurement is a good indicator of the defect level on products and the overall impact of ultrathin gate dielectric on product yield and reliability. Finally, various types of voltage screens and burn-in with duration ranging from few seconds to several hours (at wafer and packaged levels) can be implemented (at least on a selected set of products) to monitor and/ improve the reliability of the final assembly. Accordingly, the body of the text discusses the following topics: monitoring of gate dielectric reliability, monitoring of device stability, monitoring of thin dielectric initial leakage, semiconductor stress induced defects, metallic contamination, and reliability of integrated circuits.

Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics

Abstract: The degradation of 100-nm effective channel length pMOS transistors with 14 /spl Aring/ equivalent oxide thickness Jet Vapor Deposition (JVD) Si/sub 3/N/sub 4/ gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 /spl Aring/ Si/sub 3/N/sub 4/ transistors is compared to reliability of 16 /spl Aring/ SiO/sub 2/ transistors.