L
Luigi Pantisano
Researcher at Katholieke Universiteit Leuven
Publications - 163
Citations - 3916
Luigi Pantisano is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: High-κ dielectric & Gate dielectric. The author has an hindex of 34, co-authored 161 publications receiving 3767 citations. Previous affiliations of Luigi Pantisano include IMEC & Gwangju Institute of Science and Technology.
Papers
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Journal ArticleDOI
Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics
A. Kerber,E. Cartier,Luigi Pantisano,Robin Degraeve,Thomas Kauerauf,Y. Kim,A. Hou,Guido Groeseneken,Herman Maes,Udo Schwalke +9 more
TL;DR: In this paper, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows: a defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge.
Journal ArticleDOI
Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions
Michel Houssa,Luigi Pantisano,Lars-Ake Ragnarsson,Robin Degraeve,Tom Schram,Geoffrey Pourtois,S. De Gendt,Guido Groeseneken,M.M. Heyns +8 more
TL;DR: In this article, the authors give an overview of the challenges and issues pertaining to high-κ gate dielectric-based devices, including flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate wear-out and breakdown, and bias temperature instabilities.
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Evidences of oxygen-mediated resistive-switching mechanism in TiN\HfO2\Pt cells
Ludovic Goux,Piotr Czarnecki,Yang Yin Chen,Luigi Pantisano,XinPeng Wang,Robin Degraeve,Bogdan Govoreanu,Malgorzata Jurczak,Dirk Wouters,L. Altimime +9 more
TL;DR: In this paper, the influence of the Pt top-electrode thickness and of the chamber atmosphere during cell operation on the resistive switching of TiN\HfO2\Pt cells was studied.
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Passivation and interface state density of SiO2/HfO2-based/polycrystalline-Si gate stacks
TL;DR: In this paper, the authors demonstrate that a forming gas annealing temperature of 520°C significantly improves interface state passivation for SiO2/HfO2-based/polycrystalline-Si gate stacks.
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$1/f$ Noise in Drain and Gate Current of MOSFETs With High- $k$ Gate Stacks
Paolo Magnone,Felice Crupi,Gino Giusi,Calogero Pace,Eddy Simoen,Cor Claeys,Luigi Pantisano,D. Maji,V.R. Rao,Purushothaman Srinivasan +9 more
TL;DR: In this paper, the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics is investigated, and both drain-and gate-current noises are evaluated in order to obtain information about the defect content of the gate stack.