Proceedings ArticleDOI
2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner
Jun Yin,Pui-In Mak,Franco Maloberti,Rui P. Martins +3 more
- pp 48-49
TLDR
A dual-mode time-interleaved RVCO (TI-RVCO) is proposed, which offers interesting properties of extending the frequency tuning range and reducing f1/f3 corner (~1MHz → ~100kHz), resulting in a better FOM over a wide range of frequency offsets.Abstract:
Ring-VCOs (RVCOs) [1] have been avoided for over a decade for high-performance RF systems due to their much lower FOM (<165dB [2]) than that of their LC counterparts from low to high frequency offsets. Yet, as the cost of ultra-scaled CMOS technologies is escalating, the small-die-area and wide-tuning-range advantages of RVCOs have attracted more attention recently, aiming to break the FOM limit at the system level. In [2], a type-I PLL succeeds in suppressing the RVCO phase noise (PN) by extending the loop bandwidth to 10MHz (fref/20 → fref/2), facilitating an ultra-compact (0.015mm2) frequency synthesizer for 2.4GHz WLAN. However, the type-I PLL only offers 20dB/dec phase-noise suppression for its RVCO. Thus, despite using large transistors (36/0.28µm), the 1/f3 PN corner (f1/f3) is still high (∼4MHz), degrading the overall jitter performance of the PLL. This paper proposes a dual-mode time-interleaved RVCO (TI-RVCO). It offers interesting properties of extending the frequency tuning range and reducing f1/f3 corner (∼1MHz → ∼100kHz), resulting in a better FOM over a wide range of frequency offsets (10kHz to 1MHz). The achieved f1/f3 noise corner (∼90kHz to 150kHz) is comparable to the state-of-the-art LC-VCOs [3, 4].read more
Citations
More filters
Journal ArticleDOI
Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 $\times$ Frequency Edge Combiner
Xing Chen,Jacob Breiholz,Farah B. Yahya,Christopher J. Lukas,Hun-Seok Kim,Benton H. Calhoun,David D. Wentzloff +6 more
TL;DR: An all-digital ring oscillator (RO)-based Bluetooth low-energy (BLE) transmitter for ultra-low-power radios in short range Internet-of-Things (IoT) applications and proposes an RO-based solution for power and cost savings.
Journal ArticleDOI
A Time-Interleaved Ring-VCO with Reduced 1/ $\text {f}^{3}$ Phase Noise Corner, Extended Tuning Range and Inherent Divided Output
TL;DR: A time-interleaved ring-VCO (RVCO) exhibiting an improved phase noise over a wide range of frequency offsets, an extended tuning range and an inherent divided output that can be directly utilized in a PLL to save area and power is described.
Journal ArticleDOI
Design and Analysis of Low Power and High Frequency Current Starved Sleep Voltage Controlled Oscillator for Phase Locked Loop Application
TL;DR: In this paper, a current starved sleep voltage-controlled oscillator (VCO) for the Phase Locked Loop (PLL) at high frequency with low power was presented, where the sleep transistor between the pullup MOSFET and supply voltage in an inverter induces a reverse bias, causing the reduction in sub-threshold leakage current when both are in off condition.
Proceedings ArticleDOI
Ultra-Low Power Receivers for IoT Applications: A Review
TL;DR: This paper presents a review of the recent design trends and techniques in ultra-low power receivers for IoT applications.
Journal ArticleDOI
A Low Power Low Phase Noise Oscillator for MICS Transceivers.
TL;DR: A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented and a low phase noise is achieved.
References
More filters
Journal ArticleDOI
Jitter and phase noise in ring oscillators
TL;DR: A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented in this paper, where the impulse sensitivity functions are used to derive expressions for the jitter.
Journal ArticleDOI
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator
D.J. Foley,M.P. Flynn +1 more
TL;DR: In this paper, a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator are described, which employs a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs.
Proceedings ArticleDOI
CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator
D.J. Foley,M.P. Flynn +1 more
TL;DR: In this paper, a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator are described, both of which employ a self-correcting Delay Locked Loop (DLL).
Proceedings ArticleDOI
25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators
TL;DR: Noise-filtering technique and adding resistors in series with gm-device drains have shown significant reduction of the 1/f3 oscillator PN corner, however, the former needs an additional tunable inductor and the latter degrades PN in the 20dB/dec region.
Proceedings ArticleDOI
25.3 A VCO with implicit common-mode resonance
TL;DR: A new oscillator topology is introduced that resonates the common-mode of the circuit at 2×FLO, but does not require an additional inductor to achieve an oscillator noise factor of just below 2, equal to the fundamental limit of a cross-coupled LC CMOS oscillator.
Related Papers (5)
A 2-V 1.8-GHz fully-integrated CMOS dual-loop frequency synthesizer
T.K.K. Kan,Howard C. Luong +1 more