Journal ArticleDOI
A pipelined 5-Msample/s 9-bit analog-to-digital converter
Stephen H. Lewis,Paul R. Gray +1 more
TLDR
A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.Abstract:
A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.read more
Citations
More filters
Journal ArticleDOI
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
K. Bult,G.J.G.M. Geelen +1 more
TL;DR: In this article, a technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented, which is based on the concept that a very high-DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design.
Journal ArticleDOI
A 10-b 20-Msample/s analog-to-digital converter
TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Journal ArticleDOI
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Book
CMOS Data Converters for Communications
TL;DR: The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects and explains in detail how to derive data converter requirements for a given communication system.
Journal ArticleDOI
A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input
TL;DR: The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption to achieve 14-b accuracy without calibration or dithering.
References
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Journal ArticleDOI
Full-speed testing of A/D converters
TL;DR: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described.
Journal ArticleDOI
A high-performance micropower switched-capacitor filter
Rinaldo Castello,Paul R. Gray +1 more
TL;DR: A description is given of a high-performance fifth-order low-pass switched-capacitor filter operating form a single 5-V supply that uses a fully differential topology combined with input-to-output class AB amplifier design, dynamic biasing, and switched-Capacitor common-mode feedback to meet the PCM channel filter requirements.
Journal ArticleDOI
An 8-MHz CMOS subranging 8-bit A/D converter
A.G.F. Dingwall,V. Zazzu +1 more
TL;DR: In this paper, an 8-bit subranging converter (ADC) was realized in a 3/spl mu/m silicon gate, double-polysilicon capacitor CMOS process.
Journal ArticleDOI
Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter
TL;DR: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter that may be interconnected in series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates.
Journal ArticleDOI
A high-speed 7 bit A/D converter
TL;DR: A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit which results in a fully integrable A/ D function.