Proceedings ArticleDOI
8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors
Yong-Jin Lee,Min-Yong Jung,Shashank Singh,Tae-Hwang Kong,Dae-Yong Kim,Kwang-Ho Kim,Sang-Ho Kim,Jae-Jin Park,Ho-Jin Park,Gyu-Hyeong Cho +9 more
- pp 150-151
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TLDR
To reduce the number of external capacitors, one power voltage level from the PMIC is converted into a variety of power voltage levels inside the mobile AP and simplifies PCB routes, integrated low-dropout regulators (LDOs) are preferred in mobile APs.Abstract:
A modern mobile application processor (AP) requires a variety of power voltage levels, which increases the number of external capacitors around the mobile AP. This is because the supply PCB routes from the power management IC (PMIC) to the AP have parasitic inductors. The parasitic inductors introduce ripples on power voltage lines. Therefore, external capacitors are required on the PCB routes between the PMIC and the mobile AP. To reduce the number of external capacitors, one power voltage level from the PMIC is converted into a variety of power voltage levels inside the mobile AP. This both reduces external capacitors as well as the number of power pins on the mobile AP and simplifies PCB routes. For such reasons, integrated low-dropout regulators (LDOs) are preferred in mobile APs.read more
Citations
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Journal ArticleDOI
A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor
Yong-Jin Lee,Wanyuan Qu,Shashank Singh,Dae-Yong Kim,Kwang-Ho Kim,Sang-Ho Kim,Jae-Jin Park,Gyu-Hyeong Cho +7 more
TL;DR: This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity and a digital controller is implemented to prevent contentions between the two loops.
Proceedings ArticleDOI
20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V
TL;DR: A 0.5V 0.0023mm2 recursive all-digital LDO (RLDO) in 65nm with hybrid PD-SAR and PWM duty control that achieves 15.1ns and 100ns response and settling times, respectively, while maintaining 5.6mV/mA load regulation and loop stability across a 20,000× dynamic load range, eclipsing state-of-the-art active area, response time, settling time, and dynamic range metrics.
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control
TL;DR: This work presents an analog-assisted (AA) tri-loop control scheme for transient improvement, low power, and COUT reduction.
Proceedings ArticleDOI
20.6 A 0.5V-V IN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor
TL;DR: This work proposes to infuse fine-grained parallelism into ED control systems and develop a fully integrated digital LDO, which can support a larger I LOAD with a smaller COUT .
Proceedings ArticleDOI
20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor
Wen-Jie Tsou,Wen-Hau Yang,Jian-He Lin,Hsin Chen,Ke-Horng Chen,Chin-Long Wey,Ying-Hsi Lin,Shian-Ru Lin,Tsung-Yen Tsai +8 more
TL;DR: A DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation is presented.
References
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Proceedings ArticleDOI
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Journal ArticleDOI
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage
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Proceedings ArticleDOI
17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems
TL;DR: On-chip LDOs with PSR in the GHz range are in high demand for wideband optical communication systems because there is only one photo detector in the optical receiver and supply voltage variations would degrade its sensitivity severely.
Proceedings ArticleDOI
5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range
TL;DR: This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps.
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