Journal ArticleDOI
A Decorrelating Design-for-Digital-Testability Scheme for $\Sigma{-}\Delta$ Modulators
Hao-Chiao Hong,Sheng-Chuan Liang +1 more
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TLDR
A novel decorrelating design-for-digital-testability (D3T) scheme for Sigma-Delta modulators to enhance the test accuracy of using digital stimuli and has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.Abstract:
This paper presents a novel decorrelating design-for-digital-testability (D3T) scheme for Sigma-Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma-Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than -5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D3T scheme has the potential to test moderate nonlinearity. The proposed D3T scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.read more
Citations
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Journal ArticleDOI
On-Chip Support for NoC-Based SoC Debugging
TL;DR: A test wrapper and, a test and debug interface unit that enable data transfer between a tester/debugger and a core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate test anddebug.
Journal ArticleDOI
A Fully Integrated Built-In Self-Test $\Sigma{-}\Delta$ ADC Based on the Modified Controlled Sine-Wave Fitting Procedure
TL;DR: This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of the authors' knowledge.
Journal ArticleDOI
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC
Manuel J. Barragan,Rshdee Alhakim,Haralampos-G. Stratigopoulos,Matthieu Dubois,Salvador Mir,Herve Le Gall,Neha Bhargava,Ankur Bal +7 more
TL;DR: The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator, resulting in a test with a higher dynamic range that covers the full scale of the ADC.
Journal ArticleDOI
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits
Byoungho Kim,Jacob A. Abraham +1 more
TL;DR: Hardware measurement results show that this approach can be effectively used to predict the aperture jitter of a DUT, with a significant reduction in the prediction error compared with previous approaches.
Patent
Sigma-delta adc with test circuitry
TL;DR: In this article, a sigma-delta switched capacitor analog-to-digital converter (ADC) was proposed. But the ADC was not suitable for the use in the wireless communication.
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TL;DR: This chapter discusses mixed-Signal testing, which involves both direct and indirect testing of analog and mixed-signal circuits, and the challenges and benefits of using either the DSP or DAC method.
Journal ArticleDOI
Theory and applications of incremental /spl Delta//spl Sigma/ converters
TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.