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Journal ArticleDOI

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN

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TLDR
A fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN solution that reduces the area reduction by eliminating the need for an IF path is introduced.
Abstract: 
An 802.11n-draft-compliant 2times2, 2-stream MIMO radio SoC, incorporating two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface, has been integrated in a standard 0.13- mum digital CMOS technology with a die area of 36 mm2. The receiver achieves noise figures of 4 dB and 6 dB, respectively, at 2.4 GHz and 5 GHz. The transmitter EVM for a 2-stream, 40-MHz-bandwidth 64-QAM OFDM signal is - 31 dBc at 2.4 GHz and -8 dBm output power and -31.5 dBc at 5 GHz and - 4 dBm output power.

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Citations
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Proceedings ArticleDOI

MIMO transmission with residual transmit-RF impairments

TL;DR: It is demonstrated that residual distortions severely degrade the performance of (near-)optimum MIMO detection algorithms, and an efficient algorithm is proposed, which is based on an i.i.d. Gaussian model for the distortion caused by these impairments.
Posted Content

MIMO Transmission with Residual Transmit-RF Impairments

TL;DR: In this article, the effect on channel capacity and error-rate performance of residual Tx-RF impairments that defy proper compensation was studied. And the authors proposed an efficient algorithm, which is based on an i.i.d. Gaussian model for the distortion caused by these impairments.
Journal ArticleDOI

E-MiLi: Energy-Minimizing Idle Listening in Wireless Networks

TL;DR: E-MiLi employs an opportunistic downclocking mechanism to optimize the efficiency of switching clock rate, based on a simple interface to existing MAC-layer scheduling protocols, and can detect packets with close to 100 percent accuracy on the USRP software radio platform.
Proceedings ArticleDOI

E-MiLi: energy-minimizing idle listening in wireless networks

TL;DR: E-MiLi employs an opportunistic downclocking mechanism to optimize the efficiency of switching clock rate, based on a simple interface to existing MAC-layer scheduling protocols, and can detect packets with close to 100 percent accuracy on the USRP software radio platform.
Journal ArticleDOI

Supporting and Enabling Circuits for Antenna Arrays in Wireless Communications

TL;DR: Circuit techniques to control the phase and the amplitude of signals from/to each array element such that signals from those array elements can be combined and split in a desired manner for achieving high data rate communications as well as interference management.
References
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Journal ArticleDOI

All-MOS charge-redistribution analog-to-digital conversion techniques. II

TL;DR: This second paper describes a two-capacitor successive approximation technique which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at somewhat lower conversion rate.
Journal ArticleDOI

Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver

TL;DR: In this paper, the influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally.
Proceedings ArticleDOI

A 6b 600MHz 10mW ADC array in digital 90nm CMOS

D. Draxelmayr
TL;DR: A 6b converter array operates at a 600MHz clock frequency with input signals up to 600MHz and only 10mW power consumption.
Journal ArticleDOI

High-resolution A/D conversion in MOS/LSI

TL;DR: A new successive approximation analog-to-digital conversion technique compatible with most MOS process technologies is described, which combines a string of equal value diffused resistors and a binary ratioed capacitor array in a unique circuit configuration so that 12-bit monotonicity is achieved with only 8-bit ratio-accurate circuit elements.
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