A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
Kris Tiri,Ingrid Verbauwhede +1 more
- Vol. 1, pp 10246
TLDR
A novel design methodology to implement a secure DPA resistant crypto processor that combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption.Abstract:
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.read more
Citations
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Journal ArticleDOI
Introduction to differential power analysis
TL;DR: This paper examines how information leaked through power consumption and other side channels can be analyzed to extract secret keys from a wide range of devices and introduces approaches for preventing DPA attacks and for building cryptosystems that remain secure even when implemented in hardware that leaks.
Journal ArticleDOI
Fault Analysis-Based Logic Encryption
Jeyavijayan Rajendran,Huan Zhang,Chi Zhang,Garrett S. Rose,Youngok Pino,Ozgur Sinanoglu,Ramesh Karri +6 more
TL;DR: This work relates logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique that enables a designer to controllably corrupt the outputs.
Book ChapterDOI
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
Thomas Popp,Stefan Mangard +1 more
TL;DR: A novel side-channel analysis resistant logic style called MDPL is described that is a masked and dual-rail pre-charge logic style and can be implemented using common CMOS standard cell libraries, making it perfectly suitable for semi-custom designs.
Journal Article
Masked dual-rail pre-charge logic : DPA-resistance without routing constraints
Thomas Popp,Stefan Mangard +1 more
TL;DR: In this paper, a side-channel analysis resistant logic style called MDPL is proposed to avoid implementation constraints that are costly to satisfy, such as the capacitive load of complementary wires in an integrated circuit.
Book ChapterDOI
Side-channel leakage of masked CMOS gates
TL;DR: It is shown that glitches occurring in circuits of masked gates make these circuits susceptible to classical first-order DPA attacks, and a thorough theoretical analysis of the DPA-resistance of masks in the presence of glitches is provided.
References
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Book ChapterDOI
Differential Power Analysis
TL;DR: In this paper, the authors examine specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. And they also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.
Proceedings Article
A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards
TL;DR: A set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations to protect security devices such as smart cards against power attacks are built.
Book ChapterDOI
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
Kris Tiri,Ingrid Verbauwhede +1 more
TL;DR: The method employs logic gates with a power consumption, which is independent of the data signals, and therefore the technique removes the foundation for DPA, showing a perfect security whenever the layout parasitics are not taken into account.
Proceedings ArticleDOI
Energy-aware design techniques for differential power analysis protection
TL;DR: This work presents a technique, based on well-known power-reducing transformations coupled with randomized clock gating, that introduces a significant amount of scrambling in the power profile without increasing (and, in some cases, by even reducing) circuit power consumption.
Proceedings ArticleDOI
Masking the Energy Behavior of DES Encryption
H. Saputra,N. Vijaykrishnan,Mahmut Kandemir,Mary Jane Irwin,Richard R. Brooks,Soontae Kim,Wei Zhang +6 more
TL;DR: This work augment the instruction set architecture of a simple five-stage pipelined smart card processor with secure instructions to mask the energy differences due to key-related data-dependent computations in DES encryption, achieving the energy masking of critical operations consuming 83% less energy as compared to existing approaches employing dual rail circuits.