Proceedings ArticleDOI
A module generator for high speed CMOS current output digital/analog converters
R. Neff,Paul R. Gray,Alberto Sangiovanni-Vincentelli +2 more
- pp 481-484
TLDR
A module generator for Digital/Analog Converter (DAC) circuits is presented, using a combination of circuit simulation and DAC design equations to estimate performance and a new constrained optimization method is used to determine design variable values.Abstract:
This paper presents a module generator for Digital/Analog Converter (DAC) circuits. A combination of circuit simulation and DAC design equations is used to estimate performance. A new constrained optimization method is used to determine design variable values. The layout is created using stretching and tiling operations on a set of primitive cells. Close coupling of optimization and layout allows accurate incorporation of layout parasitics in optimization. Prototypes have been demonstrated for an 8-bit, 100-MHz specification, driving a 37.5-ohm video load, and a static 10-bit specification, driving a 4 mA full-scale output current. Both designs use a 5-V supply in a standard 1.2 /spl mu/m CMOS process.read more
Citations
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Journal ArticleDOI
Substrate optimization based on semi-analytical techniques
TL;DR: A three-dimensional Green's function-based boundary element method, accelerated through use of the fast Fourier transform, allows the computation of sensitivities with respect to all substrate parameters at a considerably higher speed than any methods reported in the literature.
Proceedings ArticleDOI
Layout tools for analog ICs and mixed-signal SoCs: a survey
Rob A. Rutenbar,John M. Cohn +1 more
TL;DR: This short survey enumerates briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.
Patent
High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
TL;DR: In this paper, a computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.
Proceedings ArticleDOI
Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs
TL;DR: In this article, a three-dimensional Green's Function based substrate representation, in combination with the use of the Fast Fourier Transform, significantly speeds up the computation of sensitivities with respect to all parameters associated with a given architecture and is used in a number of physical optimization tools, such as placement and trend analysis for the estimation of the impact of technology migration and/or layout re-design.
References
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A 10-b 70-MS/s CMOS D/A converter
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Proceedings ArticleDOI
CADICS-cyclic analog-to-digital converter synthesis
TL;DR: The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution, and silicon area, and performance comparable to a manual approach without using any standard cell libraries.
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