Proceedings ArticleDOI
A process-scalable low-power charge-domain 13-bit pipeline ADC
Michael P. Anthony,Edward Kohler,J. Kurtze,Lawrence J. Kushner,Gerhard Sollner +4 more
- pp 222-223
TLDR
Simulations indicate that the architecture and circuitry are well suited to scaling below 90 nm, and the prototype ADC, implemented in 0.18 mum CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step.Abstract:
A 13-bit ADC is implemented using a novel charge-domain architecture. Enhanced bucket-brigade circuitry and a tapered charge pipeline provide precision charge-domain operation in a standard CMOS process, while eliminating the need for signal-path op-amps. The prototype ADC, implemented in 0.18 mum CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step. Simulations indicate that the architecture and circuitry are well suited to scaling below 90 nm.read more
Citations
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Journal ArticleDOI
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TL;DR: The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator and the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity.
Proceedings ArticleDOI
A/D converter trends: Power dissipation, scaling and digitally assisted architectures
TL;DR: This paper summarizes recent trends in the area of low-power A/D conversion and a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.
Journal ArticleDOI
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration
Ahmed Mohamed Abdelatty Ali,Andrew Stacy Morgan,Christopher Daniel Dillon,G. Patterson,Scott Puckett,Paritosh Bhoraskar,Huseyin Dinc,M. Hensley,R. Stop,Scott Gregory Bardsley,D Lattimore,Jeff Bray,Carroll C. Speir,R. Sneed +13 more
TL;DR: A 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process with an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art.
Journal ArticleDOI
A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction
Andrea Panigada,Ian Galton +1 more
TL;DR: This work presents the first IC implementation of HDC, and the results demonstrate that HDC and DNC together enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs.
Journal ArticleDOI
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS
TL;DR: A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented to adjust the uncertain gain of the chosen residue amplifier and various other non-idealities.
References
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Journal ArticleDOI
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture
TL;DR: In this paper, a time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented, where a Nyquist rate sampling switch is used to eliminate timing skews, which is followed by subsampled, double-sampled, interleaved sample-and-hold (S/H) stages.
Journal ArticleDOI
Performance limitations of the IGFET bucket-brigade shift register
C.N. Berglund,H.J. Boll +1 more
TL;DR: In this paper, the authors show that incomplete charge transfer is an important limitation of register performance leading to signal degradation, and that by appropriate register design significantly better performance should be possible.
Journal ArticleDOI
A 9 b charge-to-digital converter for integrated image sensors
S.A. Paul,Hae-Seung Lee +1 more
TL;DR: An alternative technique for digitizing charge signals, charge-to-digital conversion, is free from many difficulties with conventional methods because A/D conversion is performed in the charge, rather than the voltage, domain.
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