A Statistical Gate-Delay Model Considering Intra-Gate Variability

TLDR: A model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability, which considers the intra-gate variability through the introduction of sensitivity constants is proposed.

Abstract: This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly influences the circuit-delay variation, it is important to characterize each gate-delay variation accurately. Furthermore, as every transistor in a gate affects the transient characteristics of the gate, it is also necessary to consider the intra-gate variability in the model of gate-delay variation. This effect is not captured in existing statistical delay analyses. The proposed model considers the intra-gate variability through the introduction of sensitivity constants. The accuracy of the model is evaluated, and some simulation results for circuit delay variation are presented.