Proceedings ArticleDOI
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
V. R. Devanathan,C.P. Ravikumar,V. Kamakoti +2 more
- pp 1-10
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TLDR
It is argued that false delay test failures can be avoided by generating "safe" patterns that are tolerant to on-chip variations, which uses process variation information, power grid topology and regional constraints on switching activity.Abstract:Â
Process variation is an increasingly dominant phenomenon affecting both power and performance in sub-100 nm technologies Cost considerations often do not permit over-designing the power supply infrastructure for test mode, considering the worst-case scenario Test application must not over-exercise the power supply grids, lest the tests will damage the device or lead to false test failures The problem of debugging a delay test failure can therefore be highly complex We argue that false delay test failures can be avoided by generating "safe" patterns that are tolerant to on-chip variations A statistical framework for power-safe pattern generation is proposed, which uses process variation information, power grid topology and regional constraints on switching activity Experimental results are provided on benchmark circuits to demonstrate the effectiveness of the frameworkread more
Citations
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Proceedings ArticleDOI
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
Hiroshi Furukawa,Xiaoqing Wen,Kohei Miyase,Yuta Yamato,Seiji Kajihara,Patrick Girard,Laung-Terng Wang,Mohammad Tehranipoor +7 more
TL;DR: CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.
Proceedings ArticleDOI
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Xiaoqing Wen,Kohei Miyase,Seiji Kajihara,Hiroshi Furukawa,Yuta Yamato,Atsushi Takashima,Kenji Noda,H. Ito,Kazumi Hatayama,Takashi Aikyo,Kewal K. Saluja +10 more
TL;DR: This paper proposes a novel and practical capture-safe test generation scheme, featuring reliable capture-safety checking and effective capture- safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation.
Journal ArticleDOI
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing
TL;DR: Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detect by the low-power test generation process.
Proceedings ArticleDOI
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation
TL;DR: This paper addresses the issue of vulnerability to IR-drop-induced yield loss in nano-scale designs with a novel per-cell dynamic IR- drop estimation method that achieves both high accuracy and high time-efficiency.
Proceedings ArticleDOI
Improved weight assignment for logic switching activity during at-speed test pattern generation
TL;DR: In this article, a new weight assignment scheme for logic switching activity was proposed, which enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model by including the power grid network structure information.
References
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Proceedings ArticleDOI
Technology scaling impact of variation on clock skew and interconnect delay
Vikas Mehrotra,Duane S. Boning +1 more
TL;DR: This work considers both random and systematic variation in interconnect and device parameters as technology scales from 180 nm to 50 nm, and shows that clock skew increases from about 15% to 30% of the clock cycle, and modeling systematic variation sources enables tighter tolerance design.
Proceedings ArticleDOI
Effects of delay models on peak power estimation of VLSI sequential circuits
TL;DR: This work would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays.
Proceedings ArticleDOI
MD-SCAN method for low power scan testing
Takaki Yoshida,Masafumi Watari +1 more
TL;DR: A new testing method named MD-SCAN (multi duty-scan) is presented which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.
Proceedings ArticleDOI
Effects of delay models on peak power estimation of VLSI sequential circuits
TL;DR: In this paper, the authors use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays.
Journal ArticleDOI
New path balancing algorithm for glitch power reduction
TL;DR: In this paper, the authors proposed an efficient path balancing algorithm to reduce power dissipation in CMOS logic circuits, which employs gate sizing and buffer insertion methods to achieve path balancing, and the ILP (integer linear program) has been employed to determine the locations of inserted buffers.