Journal ArticleDOI
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter
TLDR
An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented and achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s.Abstract:
An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-mum CMOS process. Its power dissipation is 4.64 mW from a supply voltage of 1.8 V. This active area occupies 1.2 times 0.7 mm2. The measured signal-to-noise-distortion ratio achieves 44.2 dB at an input frequency of 10 MHz. The integral nonlinearity is less than plusmn1.07 LSB, and the differential nonlinearity is less than plusmn0.72 LSB. This time-domain ADC achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s.read more
Citations
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Journal ArticleDOI
A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion
TL;DR: The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications.
Journal ArticleDOI
5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications
TL;DR: A 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate, designed for the use in radio-astronomy telescopes, for which time interleaving is not acceptable.
Journal ArticleDOI
A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS
TL;DR: The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation.
Journal ArticleDOI
A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration
TL;DR: A high resolution time-to-digital converter (TDC) architecture, which combines the advantages of sub-ranging and Vernier delay line TDCs, and a foreground DNL calibration technique is proposed to alleviate the linearity problem caused by random variations of the delays of the delay elements.
Journal ArticleDOI
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18- $\mu \text{m}$ CMOS
Liang-Jen Chen,Shen-Iuan Liu +1 more
TL;DR: Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS process are presented and the noise analysis for each TADC building block is presented.
References
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Proceedings ArticleDOI
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A 8-bit 500-KS/s low power SAR ADC for bio-medical applications
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Journal ArticleDOI
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC
Lane Gearle Brooks,Hae-Seung Lee +1 more
TL;DR: Current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed.