Journal ArticleDOI
5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications
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TLDR
A 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate, designed for the use in radio-astronomy telescopes, for which time interleaving is not acceptable.Abstract:
This paper presents a 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate. The ADC is designed for the use in radio-astronomy telescopes, for which time interleaving is not acceptable. The ADC employs a dynamic, differential voltage-to-time converter, a folded-flash time-to-digital converter (TDC), and calibration circuitry. To generate reference delays, the calibration circuitry utilizes a delay-time reference network, which is designed to map the input voltage range into 16 equal time intervals that are used for the calibration of the TDC. The 65-nm CMOS ADC achieves the Signal-to-noise plus distortion ratio/spurious-free dynamic range of 27/32 dB at Nyquist, an effective number of bits (ENOB) of 4.7 bit at low frequencies and 4.1 bit at high frequencies with a power consumption of 21.5 mW at Nyquist.read more
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Journal ArticleDOI
A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS
TL;DR: A non-interleaved 2-GS/s, 8-bit flash analog-to-digital converter (ADC) utilizing the remainder number system (RNS) quantization principle is presented, which reduces the number of comparators and thus improves the figure of merit of the flash ADC.
Proceedings Article
All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS
Robert Bogdan Staszewski,Khurram Muhammad,Dirk Leipold,Chih-Ming Hung,Yo-Chuol Ho,John Wallberg,C. Fernando,Ken Maggio,Roman Staszewski,T. Jung,Jinseok Koh,S. John,I. Deng,Vivek Sarda,O. Moreira-Tamayo,Valerian Mayega,Ran Katz,Ofer Friedman,Oren Eliezer,Elida de-Obaldia,Poras T. Balsara +20 more
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Proceedings Article
Phase noise and jitter in CMOS ring oscillators
TL;DR: In this article, a simple physically based analysis illustrates the noise processes in CMOS inverter-based and differential ring oscillators, showing that white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit.
Journal ArticleDOI
A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC
TL;DR: A novel fully time-based two-step analog-to-digital converter (ADC) is proposed that has a gain-control function to adjust the difference between the gains of the CADC and FADC due to variations in process, voltage and temperature.
Journal ArticleDOI
A 60-m Range 6.16-mW Laser-Power Linear-Mode LiDAR System With Multiplex ADC/TDC in 65-nm CMOS
TL;DR: Experimental results show that this architecture is suitable for low-cost multi-line integrated LiDAR applications compared to conventional architecture using ADC, TDC, ADC+TDC architecture.
References
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All-digital PLL and transmitter for mobile phones
Robert Bogdan Staszewski,John Wallberg,Sameh S. Rezeq,Chih-Ming Hung,Oren Eliezer,Sudheer Vemulapalli,C. Fernando,Kenneth J. Maggio,Robert B. Staszewski,N. Barton,Meng-Chang Lee,P. Cruise,Manouchehr Entezari,Khurram Muhammad,Dirk Leipold +14 more
TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
Journal ArticleDOI
Phase Noise and Jitter in CMOS Ring Oscillators
TL;DR: Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit.
Journal ArticleDOI
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS
Robert Bogdan Staszewski,Khurram Muhammad,Dirk Leipold,Chih-Ming Hung,Yo-Chuol Ho,John Wallberg,C. Fernando,Ken Maggio,Roman Staszewski,T. Jung,Jinseok Koh,S. John,I. Deng,Vivek Sarda,O. Moreira-Tamayo,Valerian Mayega,Ran Katz,Ofer Friedman,Oren Eliezer,Elida de-Obaldia,Poras T. Balsara +20 more
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
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