Proceedings ArticleDOI
An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V
K. Sawada,Y. Sugawara,S. Masui +2 more
- pp 75-76
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TLDR
In this paper, an on-chip high-voltage generator circuit for lowvoltage EEPROMs composed of a pMOSFET-based charge pump circuit driven by bootstrapped clock generators is proposed.Abstract:
We propose an on-chip high-voltage generator circuit for low-voltage EEPROMs composed of a pMOSFET-based charge pump circuit driven by bootstrapped clock generators. The voltage gain per unit stage does not suffer from the threshold voltage drop. The device implemented in a 1.2 /spl mu/m CMOS technology operates as low as 1 V.read more
Citations
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Journal ArticleDOI
MOS charge pumps for low-voltage operation
Jieh-Tsorng Wu,Kuen-Long Chang +1 more
TL;DR: In this article, a 1.2-V-to-3.5-V charge pump and a 2-V to 16-V voltage pump are demonstrated. But the limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude.
Journal ArticleDOI
A dynamic analysis of the Dickson charge pump circuit
Toru Tanzawa,T. Tanaka +1 more
TL;DR: In this paper, the authors have analyzed the Dickson charge pump circuit and derived the optimum number of stages to minimize the rise time of the output voltage and power consumption during boosting.
Journal ArticleDOI
A DC-DC charge pump design based on voltage doublers
TL;DR: In this paper, a two-phase voltage doubler and a multiphase voltage multiplier are discussed and design guidelines for the desired voltage and power levels are discussed, as well as the area requirements, the voltage gain, and the power level.
Journal ArticleDOI
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
TL;DR: The new proposed circuit with consideration of gate-oxide reliability is designed with two pumping branches and is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.
Journal ArticleDOI
A new charge pump without degradation in threshold voltage due to body effect [memory applications]
TL;DR: In this article, a new charge-pump circuit with controllable body voltage is proposed, where the back bias effect is removed and the threshold voltage of the MOSFET used as a switch is kept constant.
References
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Journal ArticleDOI
On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
TL;DR: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails.
Journal ArticleDOI
Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits
TL;DR: The characteristics of the voltage multiplier circuit are thoroughly analyzed and modeled and its capability to compensate for nonvolatile memory degradation is shown.
Proceedings ArticleDOI
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory
TL;DR: Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time at low Vcc.