Journal ArticleDOI
A dynamic analysis of the Dickson charge pump circuit
Toru Tanzawa,T. Tanaka +1 more
TLDR
In this paper, the authors have analyzed the Dickson charge pump circuit and derived the optimum number of stages to minimize the rise time of the output voltage and power consumption during boosting.Abstract:
Dynamics of the Dickson charge pump circuit are analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N/sub min/, where N/sub min/ is the minimum value of the number of stages necessary for a given parameter set of supply voltage, threshold voltage of transfer diodes, and boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results are in good agreement with simulation by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In the case of a charge pump with MOS transfer transistors, the analytical results of the rise time agree with the SPICE simulation within 10%.read more
Citations
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Journal ArticleDOI
MOS charge pumps for low-voltage operation
Jieh-Tsorng Wu,Kuen-Long Chang +1 more
TL;DR: In this article, a 1.2-V-to-3.5-V charge pump and a 2-V to 16-V voltage pump are demonstrated. But the limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude.
Journal ArticleDOI
Charge Pump Circuits: An Overview on Design Strategies and Topologies
Gaetano Palumbo,D. Pappalardo +1 more
TL;DR: In this paper, the authors provide a deep understanding of the charge pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies, and an overview of the main different topologies is also included.
Journal ArticleDOI
A DC-DC charge pump design based on voltage doublers
TL;DR: In this paper, a two-phase voltage doubler and a multiphase voltage multiplier are discussed and design guidelines for the desired voltage and power levels are discussed, as well as the area requirements, the voltage gain, and the power level.
Journal ArticleDOI
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
TL;DR: The new proposed circuit with consideration of gate-oxide reliability is designed with two pumping branches and is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.
Journal ArticleDOI
A new charge pump without degradation in threshold voltage due to body effect [memory applications]
TL;DR: In this article, a new charge-pump circuit with controllable body voltage is proposed, where the back bias effect is removed and the threshold voltage of the MOSFET used as a switch is kept constant.
References
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Journal ArticleDOI
On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
TL;DR: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails.
Journal ArticleDOI
A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure
Akira Umezawa,S. Atsumi,Masao Kuriyama,Hironori Banba,K. Imamiya,Kiyomi Naruke,S. Yamada,Etsushi Obi,Masamitsu Oshikiri,Toshihiro Suzuki,S. Tanaka +10 more
TL;DR: An experimental 4-Mb flash EEPROM has been developed based on 0.6- mu m triple- well CMOS technology in order to establish circuit technology for high-density flash memories and a newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size.
Journal ArticleDOI
Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits
TL;DR: The characteristics of the voltage multiplier circuit are thoroughly analyzed and modeled and its capability to compensate for nonvolatile memory degradation is shown.
Proceedings ArticleDOI
An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V
K. Sawada,Y. Sugawara,S. Masui +2 more
TL;DR: In this paper, an on-chip high-voltage generator circuit for lowvoltage EEPROMs composed of a pMOSFET-based charge pump circuit driven by bootstrapped clock generators is proposed.
Journal ArticleDOI
A 30 A 30 V DMOS motor controller and driver
TL;DR: In this paper, a power DMOS half bridge (R/sub on/=40 m Omega, 30-V operating voltage, 30 A peak current) for windshield-wiper motors is presented.