Proceedings ArticleDOI
Analysis on Process Variation Effect of 3D NAND Flash Memory Cell through Machine Learning Model
Jang Kyu Lee,Kyul Ko,Hyungcheol Shin +2 more
- pp 1-4
TLDR
This work investigated process variation effect of 3D NAND flash memory cell, especially about geometric variation using a machine learning (ML) model, which has multi-input and multi-output (MIMO) structure and deep hidden layers to train and predict complex data of process variation.Abstract:
We investigated process variation effect of 3D NAND flash memory cell, especially about geometric variation using a machine learning (ML) model. Geometric variability sources impact on variation of device's electrical parameters such as threshold voltage $(\mathbf{V}_{\mathbf{t}})$ , subthreshold swing (SS), transconductance $(\mathbf{g}_{\mathbf{m}})$ and on-current $(\mathbf{I}_{\mathbf{on}})$ . All these data were analyzed with 3D stochastic Technology Computer-Aided Design (TCAD) simulation and trained through ML model, which is composed of artificial neural network (ANN). The model has multi-input and multi-output (MIMO) structure and deep hidden layers to train and predict complex data of process variation. In order to make ML model more accurate, simulation for constructing training data set was carried out with a large number of random unit cells, which are cut from various strings. The completed ML model was tested with random test data set which had not been used for training to prove its accuracy. Through the test process, ML model showed the error of up to 5% and proved the accuracy of prediction.read more
Citations
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Journal ArticleDOI
Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference.
Su-in Yi,Jungsik Kim +1 more
TL;DR: In this paper, a program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference.
Proceedings ArticleDOI
Neural network aided reference voltage adaptation for NAND flash memory
TL;DR: In this paper , the authors used shallow neural networks to estimate the read reference voltages for different life-cycle conditions with the help of histogram measurements, and demonstrated that the training data for the neural networks can be enhanced by using shifted histograms, i.e., a training of the neural network is possible based on a few measurements of some extreme points used as training data.
Journal ArticleDOI
Pulse optimization and device engineering of 3D charge-trap flash for synaptic operation
TL;DR: The results of this study suggest that excellent synaptic FOMs can be attained from 3D CT nands by designing and calibrating the input pulse trains, and it has been shown that the incorporation of deeper traps through material engineering improves synaptic reliability of the3D CT cells under prolonged operations.
Journal ArticleDOI
Machine Learning-Assisted Device Modeling With Process Variations for Advanced Technology
TL;DR: In this article , a machine learning-based method for device modeling with process variations (PV), including global variation (GV) and local variation (LV), was proposed and implemented on advanced Nanosheet FETs.
References
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Proceedings ArticleDOI
Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory
Hiroyasu Tanaka,M. Kido,K. Yahashi,M. Oomura,Ryota Katsumata,Masaru Kito,Yoshiaki Fukuzumi,Motoyuki Sato,Y. Nagata,Yasuyuki Matsuoka,Yoshihisa Iwata,Hideaki Aochi,Akihiro Nitayama +12 more
TL;DR: Bit-Cost Scalable (BiCS) technology is proposed which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost.
Proceedings Article
Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory
Jae-Hoon Jang,Han-soo Kim,Wonseok Cho,Hoosung Cho,Jinho Kim,Sun Il Shim,Younggoan Jang,Jae-Hun Jeong,Byoungkeun Son,Dongwoo Kim,Kihyun,Jae-Joo Shim,Jin Soo Lim,Kyoung-hoon Kim,Su Youn Yi,Ju-Young Lim,De-will Chung,Hui-chang Moon,Sung-Min Hwang,Jong-Wook Lee,Yong-Hoon Son,U-In Chung,Won-Seong Lee +22 more
TL;DR: Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.
Proceedings ArticleDOI
Future Outlook of NAND Flash Technology for 40nm Node and Beyond
Kinam Kim,Jung-Dal Choi +1 more
TL;DR: The critical barriers in further scaling down NAND flash to 40nm technology node and beyond are reviewed and breakthrough technologies are addressed to overcome the barriers.
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