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Arithmetic Built-In Self-Test for Embedded Systems
Janusz Rajski,Jerzy Tyszer +1 more
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TLDR
This chapter discusses Built-In Self-Test, High-Level Synthesis, and Implementation-Dependent Fault Grading, which aims to improve the quality of Diagnostic Resolution in Scan-Based Designs.Abstract:
1. Built-In Self-Test. Introduction. Design for Testability. Generation of Test Vectors. Compaction of Test Responses. BIST Schemes for Random Logic. BIST for Memory Arrays. 2. Generation of Test Vectors. Additive Generators of Exhaustive Patterns. Other Generation Schemes. Two-Dimensional Generators. 3. Test-Response Compaction. Binary Adders. 1's Complement Adders. Rotate-Carry Adders. Cascaded Compaction Scheme. 4. Fault Diagnosis. Analytical Model. Experimental Validation. The Quality of Diagnostic Resolution. Fault Diagnosis in Scan-Based Designs. 5. BIST of Data-Path Kernel. Testing of ALU. Testing of the MAC Unit. Testing of the Microcontroller. 6. Fault Grading. Fault Simulation Framework. Functional Fault Simulation. Experimental Results. 7. High-Level Synthesis. Implementation-Dependent Fault Grading. Synthesis Steps. Simulation Results. 8. ABIST at Work. Testing of Random Logic. Memory Testing. Digital Integrators. Leaking Integrators. 9. Epilog. Bibliography. A. Tables of Generators. B. Assembly Language. Index.read more
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私の computer 環境
TL;DR: The longman elect new senior secondary theme book is a brand new task-based coursebook specially designed to meet the aims of the new high school curriculum for secondary 4 to 6 building on the solid foundation of knowledge skills values and attitudes laid down in the widely successful Longman elect junior secondary series as discussed by the authors.
Journal ArticleDOI
Survey of low-power testing of VLSI circuits
TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Journal ArticleDOI
Software-based self-testing methodology for processor cores
TL;DR: A new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests and demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.
Proceedings ArticleDOI
A modified clock scheme for a low power BIST test pattern generator
Patrick Girard,L. Guiller,Christian Landrault,Serge Pravossoudovitch,Hans-Joachim Wunderlich +4 more
TL;DR: A new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation and numerous advantages can be found in applying such a technique during BIST.
Journal ArticleDOI
Finite memory test response compactors for embedded test applications
TL;DR: A new class of finite memory compaction schemes called convolutional compactors (CCs) are introduced, which provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs.
References
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私の computer 環境
TL;DR: The longman elect new senior secondary theme book is a brand new task-based coursebook specially designed to meet the aims of the new high school curriculum for secondary 4 to 6 building on the solid foundation of knowledge skills values and attitudes laid down in the widely successful Longman elect junior secondary series as discussed by the authors.
Proceedings ArticleDOI
Testing embedded-core based system chips
TL;DR: An overview of current industrial practices as well as academic research in core-based IC design is provided and the challenges for future research are described.
Proceedings ArticleDOI
Towards a standard for embedded core test: an example
TL;DR: This paper provides a preliminary, unapproved view on IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language.
Proceedings ArticleDOI
Iddq test: sensitivity analysis of scaling
TL;DR: It is explained how Iddq testing becomes increasingly ineffective in the scaled product with respect to most parameters and can be improved with others.
Proceedings ArticleDOI
IDDQ and AC scan: the war against unmodelled defects
TL;DR: The effectiveness of the AC tests shows that targeting additional faults produces better quality than relying on peripheral coverage of existing tests, and all tests detect unique failures, indicating the presence of additional unmodelled faults.