Proceedings ArticleDOI
At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor
N. Tendolkar,R. Molyneaux,Carol Pyron,R. Raina +3 more
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TLDR
The novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing are presented.Abstract:
In this paper we present the novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit for issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower.read more
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Patent
Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques
TL;DR: In this paper, an embodiment of an additional functional logic circuit block, named "inter-domain on chip clock controller" (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC) of the different clock domains is presented.
Proceedings ArticleDOI
Enhanced reduced pin-count test for full-scan design
TL;DR: This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test, an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan, as well as for full-scan core-based design.
Patent
Method and apparatus for at-speed testing of digital circuits
TL;DR: In this paper, a scheme for multi-frequency at-speed logic built-in self-test (BIST) is presented, which is applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency.
References
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Journal ArticleDOI
Scan-based transition test
Jacob Savir,S. Patil +1 more
TL;DR: In this paper, several issues of skewed-load transition test are investigated, such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality.
Proceedings ArticleDOI
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
Phillip J. Nigh,David P. Vallett,A. Patel,J. Wright,Franco Motika,Donato O. Forlenza,R. Kurtulik,W. Chong +7 more
TL;DR: The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test- only" failures.
Proceedings ArticleDOI
Delay test of chip I/Os using LSSD boundary scan
TL;DR: A novel design-for-test (DFT) concept for I/O delay testing while contacting very few pads, using boundary scan and new test-generation software uncovered unique manufacturing defects of the IBM System/390 Generation 3/sup TM/ and several ASIC chips.
Proceedings ArticleDOI
Testability features of AMD-K6/sup TM/ microprocessor
TL;DR: The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests for the AMD-K6/sup TM/ microprocessor.