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Journal ArticleDOI

Contact resistance in organic transistors that use source and drain electrodes formed by soft contact lamination

Jana Zaumseil, +2 more
- 09 May 2003 - 
- Vol. 93, Iss: 10, pp 6117-6124
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TLDR
In this article, a detailed study of the electrical properties of soft contact laminations of organic transistors is presented, with an emphasis on the nature of the laminated contacts with the p-and n-type semiconductors pentacene and copper hexadecafluorophthalocyanine, respectively.
Abstract
Soft contact lamination of source/drain electrodes supported by gold-coated high-resolution rubber stamps against organic semiconductor films can yield high-performance organic transistors. This article presents a detailed study of the electrical properties of these devices, with an emphasis on the nature of the laminated contacts with the p- and n-type semiconductors pentacene and copper hexadecafluorophthalocyanine, respectively. The analysis uses models developed for characterizing amorphous silicon transistors. The results demonstrate that the parasitic resistances related to the laminated contacts and their coupling to the transistor channel are considerably lower than those associated with conventional contacts formed by evaporation of gold electrodes directly on top of the organic semiconductors. These and other attractive features of transistors built by soft contact lamination suggest that they may be important for basic and applied studies in plastic electronics and nanoelectronic systems based ...

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Citations
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Journal ArticleDOI

The larger acenes: versatile organic semiconductors.

TL;DR: New approaches to add functionality were developed to improve the processability of these materials in solution, allowing the synthesis of acenes larger than pentacene, which have hitherto been largely unavailable and poorly studied.
Journal ArticleDOI

Elastomeric Transistor Stamps: Reversible Probing of Charge Transport in Organic Crystals

TL;DR: This method, which eliminates exposure of the fragile organic surface to the hazards of conventional processing, enables fabrication of rubrene transistors with charge carrier mobilities as high as ∼15 cm2/V·s and subthreshold slopes as low as 2nF·V/decade·cm2.
Journal ArticleDOI

Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment

TL;DR: The effect of Ar plasma treatment on amorphous indium gallium zinc oxide (a-IGZO) thin films was investigated in this paper, where the authors attempted to reduce the contact resistance between the Pt∕Ti (source/drain electrode) and a-IZO (channel).
Journal ArticleDOI

42.2: World's Largest (15‐inch) XGA AMLCD Panel Using IGZO Oxide TFT

TL;DR: In this paper, the main factors affecting threshold voltage (Vth) of the IGZO thin film transistors (TFTs) are investigated and evaluated with the field effective mobility of 4.2±0.4 cm2/V-s, Vth of −1.3±1.4V and sub-threshold swing (SS) of 0.96± 0.10 V/dec.
References
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Journal ArticleDOI

High-Resolution Inkjet Printing of All-Polymer Transistor Circuits

TL;DR: It is shown that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers, and high mobilities were achieved.
Journal ArticleDOI

Paper-like electronic displays: Large-area rubber-stamped plastic sheets of electronics and microencapsulated electrophoretic inks

TL;DR: The sophistication and flexibility of the patterning procedures, high level of integration on plastic substrates, large area coverage, and good performance of the transistors are all important features of this work.
Journal ArticleDOI

Additive, nanoscale patterning of metal films with a stamp and a surface chemistry mediated transfer process: Applications in plastic electronics

TL;DR: In this paper, the authors describe a method for contact printing metal patterns with nanometer features over large areas, which relies on tailored surface chemistries to transfer metal films from the raised regions of a stamp to a substrate when these two elements are brought into intimate physical contact.
Journal ArticleDOI

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

TL;DR: In this article, the effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon thin film transistors (TFTs), and the results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance.
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