scispace - formally typeset
Search or ask a question
Proceedings ArticleDOI

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

19 Dec 2012-pp 135-139
TL;DR: A new X-filling technique to reduce the shift and capture transitions occurred during scan based test application using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced.
Abstract: In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.
Citations
More filters
Journal ArticleDOI
TL;DR: The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells and divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which provides better run length for test data reduction.

11 citations

Journal ArticleDOI
TL;DR: An efficient technique to reduce test data volume and test power simultaneously is presented and a simple decoder architecture for on-chip decompression is presented.

10 citations

Journal ArticleDOI
TL;DR: A new power transition X filling based selective Huffman encoding technique is proposed, which achieves better data compression, switching power reduction, chip area overhead reduction and speed of testing.

10 citations

Proceedings ArticleDOI
21 Feb 2013
TL;DR: This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control.
Abstract: This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control. Based on the signal transitions, which are used to control the power consumption of the Circuit under test, the clock frequency can be varied. Two different methods have been considered for controlling the scan clock frequency: using hardware control and using pre-simulated and stored test data where a dynamically controlled scan clock is used.

8 citations


Cites methods from "CSP-Filling: A New X-Filling Techni..."

  • ...The X-filling technique referred to as the ‘CSP-filling’ [13] fills the unspecified bits with logical 0’s or 1’s to reduce both shift and capture transitions occurred during scan based test application....

    [...]

Proceedings ArticleDOI
29 Apr 2013
TL;DR: A Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss and to get the required tradeoff, an adaptive type technique is utilizing.
Abstract: Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS'89 benchmark circuits' shows efficiency of the work in terms of reduction in test power.

6 citations

References
More filters
Proceedings ArticleDOI
30 Apr 2000
TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
Abstract: Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan vectors greatly increases the power dissipation for the vectors (generally the power becomes several times greater). The compacted scan vectors often can exceed the power constraints and hence cannot be used. It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced. A static compaction procedure is presented that can be used to find a minimal set of scan vectors that satisfies constraints on both average power and peak power. The proposed approach is simple yet effective and can be easily implemented in the conventional test vector generation flow used in industry today.

372 citations


"CSP-Filling: A New X-Filling Techni..." refers background in this paper

  • ...The circuit/clock modification [2], [3], [4], [5], [6] based technique are proposed by various research groups to reduce the test power....

    [...]

Proceedings ArticleDOI
26 Oct 2004
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.
Abstract: It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

285 citations

Proceedings ArticleDOI
01 Oct 2006
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Abstract: When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

247 citations


"CSP-Filling: A New X-Filling Techni..." refers methods in this paper

  • ...The probability based X-filling method, known as preferred− fill [10], where it fill’s all X-bits in the test data in one step, without doing any logic simulation....

    [...]

  • ...[7]) and X-filling technique [8], [9], [10], [11], [12], [13]....

    [...]

Journal ArticleDOI
TL;DR: A scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches and achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time.
Abstract: Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.

196 citations


"CSP-Filling: A New X-Filling Techni..." refers background in this paper

  • ..., [1]) based techniques are effective in shift power reduction, but could not reduce the capture power 2012 International Symposium on Electronic System Design...

    [...]

Proceedings ArticleDOI
29 Mar 2001
TL;DR: Experimental results are shown indicating that the proposed approach to minimizing power during scan testing can significantly reduce both logic and clock power during testing.
Abstract: A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the test set is generated and ordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from transitioning, and hence reduces switching activity in the circuit. Moreover, disabling the clock also reduces power dissipation in the clock tree which often is a major source of power. The only hardware modification that is required to implement this approach is to add the capability for the tester to gate the clock for one subset of the scan chains in the core. A procedure for generating and ordering the test set to maximize the we of scan disable is described. Experimental results are shown indicating that the proposed approach can significantly reduce both logic and clock power during testing.

159 citations


"CSP-Filling: A New X-Filling Techni..." refers background or methods in this paper

  • ...The circuit/clock modification [2], [3], [4], [5], [6] based technique are proposed by various research groups to reduce the test power....

    [...]

  • ...This includes clock gating [3], scan enable disabling [4], virtual circuit partitioning [5], scan cell modification [6]....

    [...]