Proceedings ArticleDOI
CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications
S. Sivanantham,K. Sarathkumar,J. P. Manuel,Partha Sharathi Mallick,J. R. P. Perinbam +4 more
- pp 135-139
TLDR
A new X-filling technique to reduce the shift and capture transitions occurred during scan based test application using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced.Abstract:
In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.read more
Citations
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Journal ArticleDOI
Two-stage low power test data compression for digital VLSI circuits
K. Thilagavathi,S. Sivanantham +1 more
TL;DR: The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells and divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which provides better run length for test data reduction.
Journal ArticleDOI
Low-power selective pattern compression for scan-based test applications
TL;DR: An efficient technique to reduce test data volume and test power simultaneously is presented and a simple decoder architecture for on-chip decompression is presented.
Journal ArticleDOI
Power transition X filling based selective Huffman encoding technique for test-data compression and Scan Power Reduction for SOCs
TL;DR: A new power transition X filling based selective Huffman encoding technique is proposed, which achieves better data compression, switching power reduction, chip area overhead reduction and speed of testing.
Proceedings ArticleDOI
Adaptive test clock scheme for low transition LFSR and external scan based testing
TL;DR: This paper presents an approach to reduce the test time of an external test applied from an automatic test equipment by speeding up low activity cycles, keeping the power under control.
Proceedings ArticleDOI
Adaptive Low Power RTPG for BIST based test applications
TL;DR: A Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss and to get the required tradeoff, an adaptive type technique is utilizing.
References
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Proceedings ArticleDOI
Static compaction techniques to control scan vector power dissipation
TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
Proceedings ArticleDOI
Minimizing power consumption in scan testing: pattern generation and DFT techniques
TL;DR: Case study information on ATPG- and DFT-based solutions for test power reduction is presented and ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test.
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Journal ArticleDOI
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction
TL;DR: A scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches and achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time.
Proceedings ArticleDOI
Reducing power dissipation during test using scan chain disable
TL;DR: Experimental results are shown indicating that the proposed approach to minimizing power during scan testing can significantly reduce both logic and clock power during testing.
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