Journal ArticleDOI
A Reduced Complexity Wallace Multiplier Reduction
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TLDR
A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction, producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.Abstract:
Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.read more
Citations
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Proceedings ArticleDOI
Design of an algorithmic Wallace multiplier using high speed counters
Shahzad Asif,Yinan Kong +1 more
TL;DR: The proposed algorithm can be used to implement the efficient counter based Wallace multiplier of any size suitable for FPGA or ASIC synthesis tools and is up to 22% faster as compared to the traditional Wallace multiplier.
Proceedings ArticleDOI
Low power wallace tree multiplier using modified full adder
TL;DR: A modified full adder using multiplexer is proposed to achieve low power consumption of multiplier and shows an average reduction of 37.45% in power consumption, 45.75% in area, and 17.65% in delay compared to the existing approaches.
Journal ArticleDOI
Low-Area wallace multiplier
Shahzad Asif,Yinan Kong +1 more
TL;DR: Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers, without compromising on the speed of the original Wallace multiplier.
Book ChapterDOI
An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders
M. Sakthimohan,J. Deny +1 more
TL;DR: In this paper, a Wallace tree 8 * 8 multiplier architecture is proposed, and it produces optimized area and delay, where 2-bit and 3-bit adders are utilized in the 8-bit multiplier.
Proceedings ArticleDOI
Efficient fast convolution architectures for convolutional neural network
TL;DR: A fully parallel architecture with high throughput based on the fast convolution algorithm and its matrix form is proposed and output data reuse scheme corresponding to CNN is considered to further increase efficiency and reduce computation redundancy.
References
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Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Book
Computer Arithmetic: Algorithms and Hardware Designs
TL;DR: An indispensable resource for instruction, professional development, and research, Computer Arithmetic: Algorithms and Hardware Designs, Second Edition combines broad coverage of the underlying theories of computer arithmetic with numerous examples of practical designs, worked-out examples, and a large collection of meaningful problems.
Proceedings ArticleDOI
A comparison of Dadda and Wallace multiplier delays
TL;DR: In this paper, a detailed analysis for several sizes of Wallace and Dadda multipliers is presented, and it is shown that despite the presence of a larger carry propagating adder, their design yields a slightly faster multiplier.
Proceedings ArticleDOI
The engineering design of the stretch computer
TL;DR: This computer, like the 704, is aimed at scientific problems such as reactor design, hydrodynamics problems, partial differential equations etc., its instruction set and organization are such that it can handle with ease data-processing problems normally associated with commercial applications, such as processing of alphanumeric fields, sorting, and decimal arithmetic.
Journal ArticleDOI
Parallel reduced area multipliers
TL;DR: Reduced Area multipliers are presented, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers.