Design of a 3rd-Order Single-Loop 1-Bit Discrete Time ∑-ΔModulator

TLDR: A 3rd-order single-loop 1-bit discrete time (DT) ∑-Δ modulator is designed and implemented in a 40-nm CMOS process and a simple pure dynamic comparator is used to save power consumption.

Abstract: A 3rd-order single-loop 1-bit discrete time (DT) ∑-Δ modulator is designed and implemented in a 40-nm CMOS process. The single-loop 1-bit topology is selected because it is less sensitive to non-idealities of the devices and consumes less power. As a result of design optimization, the order is set to 3 and the oversampling ratio (OSR) is chosen to 128. The value of sampling capacitor is set to 2.6 pF to satisfy the noise requirements. In order to adapt low-voltage environment, the two-stage operational amplifier is implemented in the integrator instead of the cascode architecture. Since the design requirement for the comparator is not stringent in the modulator, a simple pure dynamic comparator is used to save power consumption. The simulated output spectrum show that the proposed modulator achieves a peak signal to noise ratio (SNR) of 87.9 dB in the signal bandwidth of 100 kHz with the sampling frequency of 25 MHz. The total power consumption is 2.1 mW under a 1.2-V supply.