Journal ArticleDOI
Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology
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TLDR
In this paper, a novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs) was proposed to enhance the hardness of the single event upset.Abstract:
The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).,To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.,To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.,The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.read more
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Journal ArticleDOI
Design of quaternary MIN and MAX circuits using graphene nanoribbon field effect transistors
TL;DR: In this article , the GNRFET based quaternary minimum (MIN) and maximum (MAX) circuits are developed to ensure the functionality of the digital circuits, the proposed designs are simulated extensively in HSPICE tool for performance analysis, they optimized by 67.13%, 18.7%, 73.16% and 25.88% in power consumption, delay, power delay product (PDP) and circuit area, respectively.
Journal ArticleDOI
Design of bilayer graphene nanoribbon tunnel field effect transistor
Ramesh Kumar Vobulapuram,Javid Basha Shaik,P Venkatramana,Durga Prasad Mekala,Ujwala Lingayath +4 more
TL;DR: In this article, the authors proposed a tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs) for future low power very large-scale integration (VLSI) devices.
Journal ArticleDOI
Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques
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Journal ArticleDOI
Carbon nanotube computer
Max M. Shulaker,Gage Hills,Nishant Patil,Hai Wei,Hong-Yu Chen,H.-S. Philip Wong,Subhasish Mitra +6 more
TL;DR: This experimental demonstration is the most complex carbon-based electronic system yet realized, and a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field effect transistors (CNFETs) is presented.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE, including elastic scattering in the channel region, resistive source/drain (S/D), Schottky-barrier resistance, and parasitic gate capacitances.
Journal ArticleDOI
Chirality-specific growth of single-walled carbon nanotubes on solid alloy catalysts
Feng Yang,Xiao Wang,Daqi Zhang,Juan Yang,Da Luo,Ziwei Xu,Jiake Wei,Jian-Qiang Wang,Zhi Xu,Fei Peng,Xuemei Li,Ruoming Li,Yilun Li,Meihui Li,Xuedong Bai,Feng Ding,Yan Li +16 more
TL;DR: It is shown that SWNTs of a single chirality, (12, 6), can be produced directly with an abundance higher than 92 per cent when using tungsten-based bimetallic alloy nanocrystals as catalysts, unlike other catalysts used so far, which have such high melting points that they maintain their crystalline structure during the chemical vapour deposition process.
Journal ArticleDOI
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.