Journal ArticleDOI
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
TLDR
A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.Abstract:
This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.read more
Citations
More filters
Journal ArticleDOI
Design of energy-efficient and robust ternary circuits for nanotechnology
TL;DR: These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes, which makes them very suitable for the multiple- V t design method.
Journal ArticleDOI
Design of a Ternary Memory Cell Using CNTFETs
TL;DR: In this paper, a ternary memory cell based on carbon nanotube field effect transistors (CNTFETs) is proposed, which uses a transmission gate for the write operation and a buffer for the read operation to make them separate.
Journal ArticleDOI
Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs
TL;DR: A new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs) and they show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay.
Journal ArticleDOI
Residue Number Systems: A New Paradigm to Datapath Optimization for Low-Power and High-Performance Digital Signal Processing Applications
TL;DR: The aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications by investigating how this unconventional number system can be leveraged to benefit their implementation.
Journal ArticleDOI
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits
Mohammad Hossein Moaiyeri,Reza Faghih Mirzaee,Akbar Doostaregan,Keivan Navi,Omid Hashemipour +4 more
TL;DR: Improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits are demonstrated.
References
More filters
Journal ArticleDOI
Logic circuits with carbon nanotube transistors
TL;DR: This work demonstrates logic circuits with field-effect transistors based on single carbon nanotubes that exhibit a range of digital logic operations, such as an inverter, a logic NOR, a static random-access memory cell, and an ac ring oscillator.
Journal ArticleDOI
Growth of Single-Walled Carbon Nanotubes from Discrete Catalytic Nanoparticles of Various Sizes
TL;DR: In this article, the diameters of single-walled carbon nanotubes are determined by their diameters in the cores of catalytic nanoparticles with diameters between 1−2 nm and 3−5 nm.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field effect transistors (CNFETs) is presented.
Journal ArticleDOI
Theory of ballistic nanotransistors
TL;DR: In this paper, numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors, and the model reduces to Natori's theory of the ballistic MOSFET.
Related Papers (5)
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
Jie Deng,Hon-Sum Philip Wong +1 more
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking
Jie Deng,Hon-Sum Philip Wong +1 more
Carbon-nanotube-based voltage-mode multiple-valued logic design
Arijit Raychowdhury,Kaushik Roy +1 more