Design of Low-Power DSP-Free Coherent Receivers for Data Center Links

TLDR: This work proposes and evaluates low-power DSP-free homodyne coherent receiver architectures for dual-polarization quadrature phase shift keying (DP-QPSK) for inter- and intradata center links, and proposes a novel optical polarization demultiplexing technique, for DP- QPSK and higher-order modulation formats.

Abstract: Coherent detection offers high spectral efficiency and receiver sensitivity, but digital signal processing (DSP)-based coherent receivers may be prohibitively power hungry for data centers even when optimized for short-reach applications, where fiber propagation impairments are less severe. We propose and evaluate low-power DSP-free homodyne coherent receiver architectures for dual-polarization quadrature phase shift keying (DP-QPSK) for inter- and intradata center links. We propose a novel optical polarization demultiplexing technique, for DP-QPSK and higher-order modulation formats, with three cascaded phase shifters driven by marker tone detection circuitry. We consider carrier recovery based on either optical or electrical phase-locked loops (PLLs). We propose a novel multiplier-free phase detector based on XOR gates, which exhibits less than 0.5 dB power penalty relative to a conventional Costas loop phase detector. We also study the relative performance of homodyne DP-differential QPSK, for which carrier phase recovery is unnecessary. Our proposed DSP-free architectures exhibit ∼1 dB power penalty at small chromatic dispersion compared to their DSP-based counterparts. We estimate conservatively that the high-speed analog electronics of an electrical PLL-based coherent receiver consume nearly 4 W for 200 Gbit/s DP-QPSK, assuming a 90-nm complementary metal-oxide semiconductor process.