Proceedings ArticleDOI
Detecting SEU-caused routing errors in SRAM-based FPGAs
E.S.S. Reddy,Vikram Chandrasekhar,M. Sashikanth,V. Kamakoti,N. Vijaykrishnan +4 more
- pp 736-741
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TLDR
A new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA is proposed and it is noteworthy that the time required for error detection is independent of both the number of switch matrices and thenumber of logic blocks in the FPN.Abstract:
This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.read more
Citations
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Journal ArticleDOI
Field Programmable Gate Array Applications—A Scientometric Review
TL;DR: This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGA from 1992 to 2018, finding the top 150 applications that are divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications.
Journal ArticleDOI
Understanding radiation effects in SRAM-based field programmable gate arrays for implementing instrumentation and control systems of nuclear power plants
TL;DR: In this paper, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGA, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities.
Proceedings ArticleDOI
Single-event-upset (SEU) awareness in FPGA routing
S. Golshan,Eli Bozorgzadeh +1 more
TL;DR: A SEU-aware routing algorithm is presented that provides significant reduction in bridging faults caused by SEUs and in asymmetric SRAM FPGA using the authors' router average FIT (failure-in-time) rate is reduced by 36%.
Proceedings ArticleDOI
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
TL;DR: The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.
Journal ArticleDOI
A Review on SEU Mitigation Techniques for FPGA Configuration Memory
TL;DR: The mitigation techniques for SEUs in the configuration memory of SRAM-based FPGAs, as the configurationMemory is highly susceptible to SEUs, are reviewed.
References
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Book ChapterDOI
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz,Jonathan Rose +1 more
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Proceedings ArticleDOI
A deductive technique for diagnosis of bridging faults
TL;DR: A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits.
Proceedings ArticleDOI
Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems
TL;DR: This work presents an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to be used in high-reliability and high-availability hardware and ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing.
Proceedings ArticleDOI
Novel technique for built-in self-test of FPGA interconnects
TL;DR: This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding, which has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources.
Proceedings ArticleDOI
A deductive technique for diagnosis of bridging faults
Venkataraman,Fuchs +1 more
TL;DR: In this paper, a deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits.