Proceedings ArticleDOI
Development of self-assembled 3-D integration technology and study of microbump and TSV induced stress in thinned chip/wafer
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TLDR
Li et al. as mentioned in this paper proposed and demonstrated the self-assembly technology that uses liquid surface tension to create a 3D super-chip, which is strongly required to remove the remaining stress in the thinnd Si chip/wafer.Abstract:
We have proposed and demonstrated the self-assembly technology that uses liquid surface tension to create a 3-D super-chip. Lots of chips can be simultaneously, precisely, and quickly aligned onto wafers with the self-assembly. We also studied the mechanical stress remained in the thinned Si chip/wafer using 2D micro-Raman spectroscopy. The measurement results pointed out that both metal micorbumps and TSVs induced the compressive and tensile stress in the thinned Si, and they might cause serious problems to 3-D LSIs. It is strongly required to remove the remaining stress in the thinnd Si chip/wafer.read more
Citations
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Journal ArticleDOI
Relation between Raman frequency and triaxial stress in Si for surface and cross-sectional experiments in microelectronics components
TL;DR: In this paper, different ways to calculate the relation between Raman frequency and triaxial stress, and the related Raman peak intensities, are discussed in detail, and a detailed description explaining how to calculate a relation between the silicon Raman frequencies and local stress or strain in the silicon, applied to stress measurements in microelectronics.
Proceedings ArticleDOI
In-depth Raman spectroscopy analysis of various parameters affecting the mechanical stress near the surface and bulk of Cu-TSVs
TL;DR: In this paper, a discussion of the relation between the observed Raman shift and the various stress tensor components is given, showing that this relation is often wrongly applied, and that in many cases the compressive stress along the vertical axis of the TSV, dominates the Raman results and hides the tensile axial component which is of most relevance for its impact on CMOS devices.
Patent
Method for Self-Assembly of Substrates and Devices Obtained Thereof
TL;DR: In this paper, a method for defining regions with different surface liquid tension properties on a substrate is disclosed, which includes: providing a substrate with a main surface having a first surface liquid-tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed surface exposed; patterning the exposed seed layer to expose the main surface.
References
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Journal ArticleDOI
Future system-on-silicon LSI chips
TL;DR: In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Proceedings ArticleDOI
Three-dimensional shared memory fabricated using wafer stacking technology
K. W. Lee,T. Nakamura,Teruo Ono,Yusuke Yamada,T. Mizukusa,H. Hashimoto,Ki-Tae Park,Hiroyuki Kurino,Mitsumasa Koyanagi +8 more
TL;DR: It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
Proceedings ArticleDOI
Neuromorphic vision chip fabricated using three-dimensional integration technology
Mitsumasa Koyanagi,Yoshihiro Nakagawa,K. W. Lee,T. Nakamura,Y. Yamada,K. Inamura,Ki-Tae Park,Hiroyuki Kurino +7 more
TL;DR: In this paper, a 3D integration technology for image processing and pattern recognition with parts of functions of the retina and visual cortex using silicon is presented. And the three-dimensional (3D) integration technology achieved an image processing, pattern recognition, and pattern classification system using parts of functional units of the human brain using silicon.
Proceedings ArticleDOI
Intelligent image sensor chip with three dimensional structure
Hiroyuki Kurino,Kang-Wook Lee,T. Nakamura,Katsuyuki Sakuma,Ki-Tae Park,Nobuaki Miyakawa,Shimazutsu Hiroaki,K.Y. Kim,K. Inamura,Mitsumasa Koyanagi +9 more
TL;DR: A 3D image sensor test chip was fabricated using this 3D integration technology in this paper, and basic electric characteristics were evaluated in the test chip using the three-dimensional integration technology.