Journal ArticleDOI
Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication
Jose Anup P,Kenneth L. Shepard +1 more
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TLDR
Negative impedance converters inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/ mm at 10 GHz, a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width.Abstract:
In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18-mum CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER<10-14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire widthread more
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Proceedings ArticleDOI
Firefly: illuminating future network-on-chip with nanophotonics
TL;DR: Firefly is a hybrid, hierarchical network architecture that consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using nanophotonics - exploiting the benefits of electrical signaling for short, local communication while nanophotinics is used only for global communication to realize an efficient on-chip network.
Journal ArticleDOI
Energy-efficient networking: past, present, and future
TL;DR: Some of the motivations driving the need for energy-efficient communications are presented and some of the recent techniques and solutions that have been proposed to minimize energy consumption are described and discussed.
Proceedings ArticleDOI
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
TL;DR: This paper proposes three silicon-photonic network designs that provide low-power, high-bandwidth inter-die communication: a static wavelength-routed point-to-point network, a "two-phase" arbitrated network, and a limited-connectivity point- to- point network.
Proceedings ArticleDOI
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
TL;DR: A novel NoC with hybrid interconnect that leverages multiple types of interconnects - specifically, conventional full-swing short-range wires for the data path, in conjunction with low-swing, multi-drop wires with long-range, ultra-low-latency communication for the flow control signals.
Journal ArticleDOI
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
Jri Lee,Ke-Chung Wu +1 more
TL;DR: A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described, revealing rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 231 -1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.
References
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The future of wires
R. Ho,Ken Mai,Mark Horowitz +2 more
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
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Low-jitter and process independent DLL and PLL based on self biased techniques
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.
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A 160 MHz 32 b 0.5 W CMOS RISC microprocessor
J. Montanaro,R. Witek,K. Anne,A.J. Black,Elizabeth M. Cooper,Daniel W. Dobberpuhl,P. Donahue,J. Eno,A. Farell,G. Hoeppner,D. Kruckemyer,Thomas H. Lee,P. Lin,L. Madden,Daniel C. Murray,M. Pearce,S. Santhanam,K. Snyder,R. Stephany,S.C. Thierauf +19 more
TL;DR: This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply and Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board.
Journal ArticleDOI
Transistor Negative-Impedance Converters
TL;DR: The physical characteristics of transistors, compactness, long life, simple power requirements, plus constancy of pertinent electrical parameters enhance their practical utility in the production of negative impedances.