Journal ArticleDOI
High Speed and Low Energy Capacitively Driven On-Chip Wires
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TLDR
The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers.Abstract:Â
We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8x over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5x. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7x using a 200 mV swing.read more
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Book
On-Chip Networks
TL;DR: Various fundamental aspects of on-chip network design are examined and the reader is provided with an overview of the current state-of-the-art research in this field.
Proceedings ArticleDOI
High-Speed and Low-Energy Capacitively-Driven On-Chip Wires
TL;DR: The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers.
Journal ArticleDOI
Low-Power, High-Speed Transceivers for Network-on-Chip Communication
TL;DR: This paper presents a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate.
Journal ArticleDOI
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects
TL;DR: A set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs using an s-parameter wire-pair model and shows that a driver with series capacitance and a resistive load are fair approximations of these ideal terminations in the frequency range of interest.
Proceedings ArticleDOI
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
TL;DR: A novel NoC with hybrid interconnect that leverages multiple types of interconnects - specifically, conventional full-swing short-range wires for the data path, in conjunction with low-swing, multi-drop wires with long-range, ultra-low-latency communication for the flow control signals.
References
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Journal ArticleDOI
The future of wires
R. Ho,Ken Mai,Mark Horowitz +2 more
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Journal ArticleDOI
Power distribution system design methodology and capacitor selection for modern CMOS technology
TL;DR: In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Journal ArticleDOI
Improved sense-amplifier-based flip-flop: design and measurements
Borivoje Nikolic,Vojin G. Oklobdzija,Vladimir Stojanovic,Wenyan Jia,James Kar Shing Chiu,M. Ming-Tak Leung +5 more
TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.
Journal ArticleDOI
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
D. Pham,T. Aipperspach,David William Boerstler,M. Bolliger,Rajat Chaudhry,D. Cox,P. Harvey,Paul Marlan Harvey,Harm Peter Hofstee,Charles Ray Johns,J. Kahle,Atsushi Kameyama,J. Keaty,Y. Masubuchi,Mydung Pham,J. Pille,S. Posluszny,Mack W. Riley,Daniel Lawrence Stasiak,Masakazu Suzuoki,Osamu Takahashi,James D. Warnock,S. Weitzel,D. Wendel,Kazuaki Yazawa +24 more
TL;DR: In this paper, the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends, are reviewed, and a first-generation Cell processor is described.
Journal ArticleDOI
Transmitter equalization for 4-Gbps signaling
William J. Dally,John W. Poulton +1 more
TL;DR: 0.5-micron CMOS transmitter and receiver circuits that use active equalization to overcome the frequency-dependent attenuation of copper lines are developed.