Journal ArticleDOI
Trench DMOS transistor technology for high-current (100 A range) switching
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TLDR
In this article, the authors present the development of rugged high-current (100 A range) low-voltage trench DMOS transistors, featuring 4 mΩ on-resistance, with controlled bulk avalanche breakdown at 70 V and gate dielectric breakdown at 60 V.Abstract:
Design and processing concepts are presented that have led to the development of rugged high-current (100 A range) low-voltage trench DMOS transistors, featuring 4 mΩ on-resistance, with controlled bulk avalanche breakdown at 70 V and gate dielectric breakdown at 60 V. The results of a simulation-based investigation are also presented, revealing that the trench DMOS technology has at least a factor-of-two die area advantage over its planar DMOS counterpart in the range from low (50 V) to medium (200 V) voltages.read more
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Patent
Power semiconductor devices and methods of manufacture
Ashok Challa,Alan Elbanhawy,Thomas E. Grebs,Nathan Kraft,Dean E. Probst,Rodney S. Ridley,Steven Sapp,Qi Wang,Chongman Yun,J.G. Lee,Peter H. Wilson,Joseph A. Yedinak,J.Y. Jung,Hocheol Jang,Babak S. Sani,Richard Stokes,Gary M. Dolny,John Mytych,Becky Losee,Adam Selsley,Robert Herrick,James J. Murphy,Gordon K. Madson,Bruce D. Marchant,Christopher L. Rexer,Christopher Boguslaw Kocon,Debra S. Woolsey +26 more
TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.
Journal ArticleDOI
SiC devices: physics and numerical simulation
M. Ruff,H. Mitlehner,R. Helbig +2 more
TL;DR: In this article, the important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6HSiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities.
Patent
Silicon carbide power mosfet with floating field ring and floating field plate
TL;DR: In this paper, the first and second silicon carbide layers are used to form a floating field ring in the termination region of a power MOSFET. But the floating field rings are not used in this paper.
Patent
Dual trench power MOSFET
TL;DR: In this paper, a MOSFET includes a first semiconductor region of a first conductivity type, a gate trench which extends into the first semiconductors region, and a source trench, which is laterally spaced from the gate trench.
Patent
Superjunction Structures for Power Devices and Methods of Manufacture
Joseph A. Yedinak,Christopher L. Rexer,Mark L. Rinehimer,Praveen Muraleedharan Shenoy,Jaegil Lee,Hamza Yilmaz,Chong-Man Yun,Dwayne S. Reichl,James Pan,Rodney S. Ridley,Harold Heidenreich +10 more
TL;DR: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type as discussed by the authors, and each of the plurality of pillars of second conductivities type further includes an implant portion filled with semiconductor material.
References
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Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Modern power devices
TL;DR: In this article, the authors introduce the concept of field effect transistors in the context of rectifier concepts and introduce a new Rectifier concept called Field Effect Transistor (FET) this article.
Patent
Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
TL;DR: In this article, a power MOSFET was used to suppress voltage breakdown near the gate using a polygon-shaped trench in which the gate was positioned, using a shaped deep body junction that partly lies below the trench bottom, and special procedures for growth of gate oxide at various trench corners.
Journal ArticleDOI
The Oxidation of Shaped Silicon Surfaces
R. B. Marcus,T. T. Sheng +1 more
TL;DR: In this article, a 30% decrease in oxide thickness at silicon step edges following 900° and 950°C wet oxidation is attributed to the effect of locally compressive intrinsic stress within the oxide on the solubility of oxygen.
Journal ArticleDOI
The COMFET—A new high conductance MOS-gated device
TL;DR: In this article, a new MOS gate-controlled power switch with a very low on-resistance is described, which employs an n-epitaxial layer grown on a p+substrate.