Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition

TLDR: A low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs) that can be implemented on a moderate hardware cost with low power dissipation.

Abstract: This paper presents a low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs). Both estimation and correction algorithms share the common derivative filter, which makes them possible to reduce the chip area. Furthermore, these algorithms use the polyphase filtering technique and do not use adaptive digital synthesis filters. Thus, the proposed calibration can be implemented on a moderate hardware cost with low power dissipation. The adopted feedforward technology eliminates the stability issues encountered with the adaptive technique. The Hardware Description Language (HDL) design of the proposed calibration is synthesized using a 28nm FD-SOI process for a 60dB SNR TIADC clocked at 2.7GHz. The calibration is designed for both baseband and sub-sampling TIADC applications. For sub-sampling TIADCs with the input at the first four Nyquist bands, the synthesized calibration system occupies $0.04\rm {mm}^{2}$ of area and dissipates a total power of 33.2mW. For the baseband TIADC applications, it occupies $0.02\rm {mm}^{2}$ and consumes 15.5mW.