Aalborg Universitet
Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV
SiC MOSFET enabled MV converter
Dalal, Dipen Narendra; Christensen, Nicklas; Jørgensen, Asger Bjørn; Sønderskov, Simon
Dyhr; Beczkowski, Szymon; Uhrenfeldt, Christian; Munk-Nielsen, Stig
Published in:
Proceedings of 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)
DOI (link to publication from Publisher):
10.23919/EPE17ECCEEurope.2017.8099274
Publication date:
2017
Document Version
Accepted author manuscript, peer reviewed version
Link to publication from Aalborg University
Citation for published version (APA):
Dalal, D. N., Christensen, N., Jørgensen, A. B., Sønderskov, S. D., Beczkowski, S., Uhrenfeldt, C., & Munk-
Nielsen, S. (2017). Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC
MOSFET enabled MV converter. In Proceedings of 2017 19th European Conference on Power Electronics and
Applications (EPE'17 ECCE Europe) IEEE Press. https://doi.org/10.23919/EPE17ECCEEurope.2017.8099274
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Gate driver with high common mode rejection and self turn-on mitigation
for a 10 kV SiC MOSFET enabled MV converter
Dipen Narendra Dalal, Nicklas Christensen, Asger Bjørn Jørgensen, Simon Dyhr Sønderskov,
Szymon Beczkowski, Christian Uhrenfeldt, Stig Munk-Nielsen
Department of Energy Technology
Aalborg University
Pontopidastræde 111
Aalborg 9220, Denmark
{dnd,nic,abj,sds,sbe,chu,smn}@et.aau.dk
http://www.et.aau.dk
Acknowledgments
This work is supported by the IEPE platform project funded by Innovation Fund, Denmark and grant
from Obel Family Foundation.
Keywords
Wide bandgap devices, Silicon Carbide (SiC), MOSFET, New switching devices,
EMC/EMI
Abstract
This paper investigates gate driver design challenges encountered due to the fast switching transients in
medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a
reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller
clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate
driver circuit are verified in a double pulse test setup and a continuous switching operation using the
10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification and
detailed test results are presented to validate the gate driver functionality. The designed gate driver circuit
shows satisfactory performance with increased common mode noise immunity and protection against the
Miller current induced unwanted turn on.
Introduction
Medium voltage (MV) silicon carbide (SiC) MOSFETs are emerging as promising devices due to their
capability of blocking higher voltages and switching at higher frequencies with increased thermal con-
ductivity compared to their Silicon (Si) counterparts [1]. With latest technological improvements these
devices are reaching the level of maturity to be considered for medium voltage and high power conver-
sion applications e.g., solid state transformer [2]. Considering high dv/dt switching transients, intrinsic
device parasitics together with parasitic capacitance external to the device are crucial and require careful
optimization to utilize SiC MOSFETs at their full potential [3], [4]. In a half bridge power module, the
mid-point experiences high dv/dt during switching transients. The isolation barriers inside the power
modules and interfacing circuitry which experiences the dv/dt, introduces the common mode (CM) cur-
rents due to capacitive coupling. One of the dominant paths for this CM current is through an isolation
barrier of the DC-DC power supply of high side (HS) gate driver circuit as graphically illustrated in
Fig. 1. For reliable operation, and in order to maintain the gate driver control signal fidelity, this CM
current needs to be attenuated. The magnitude of the CM current is directly affected by the dv/dt and
isolation capacitance (C
iso
) based on (1).
i
cm
= C
iso
·
dv
dt
(1)
Gate
Driver
C
iso
V
in
+20 V
-5 V
i
cm
DC+
DC-
OUT
+20/-5 V
Isolated
Power supply
high
dV/dt
Fig. 1: Schematic representation of common mode current path for the high side gate driver power supply
Fast switching transients in the MV SiC MOSFETs can result in dv/dt as high as 30 kV/µs, which
imposes the requirement for a very low isolation capacitance (< 5 pF) in the gate driver circuitry [5].
Readily available galvanically isolated power supplies and driver integrated circuits (ICs) with target
application for 6.5 kV IGBTs limits its application for SiC devices with voltage rating of 10 kV and
higher. Furthermore, commercially available regulated isolated power supplies with insulation voltage
rating of 10 kV or above has an isolation capacitance in the range of 10–20 pF [6]. Recent publications
have demonstrated a gate driver power supply for 10 kV SiC MOSFETs/15 kV SiC IGBTs. These are
unregulated, which requires an additional stage to achieve voltage regulation [7],[8]. In addition to the
CM current, the high dv/dt switching transients can induce undesirable turn on in a half bridge power
module due to the Miller effect, when the complementary switch is turning on [9]. Taking these above
mentioned considerations into account, this paper presents the design of a regulated power supply with
an isolation capacitance of 2.6 pF and a gate driver circuit that incorporates an active Miller clamp
functionality for stably driving a 10 kV SiC MOSFET.
DC-DC isolated power supply
This section presents the design of a regulated DC-DC isolated power supply. Design considerations for
the high insulation voltage and low isolation capacitance transformer are also discussed with measured
key parameters.
Power supply topology
Fig. 2: Schematic of a designed flyback converter
Fig. 3: Schematic of (a) primary switch and (b) sec-
ondary snubber circuit
The designed power supply utilises a flyback topology with dual secondary windings as shown in Fig. 2.
In order to achieve compact size, a flyback controller IC (LT8302) with an integrated switch is chosen.
The IC operates in boundary conduction mode (BCM) or discontinuous conduction mode (DCM) with
a variable switching frequency (12 to 400 kHz) and regulates the output voltage by sensing transformer
primary winding voltage. Voltage regulation based on primary side sensing eliminates the need of a
feedback circuitry from secondary side i.e optocoupler, which would contribute as an additional isolation
capacitance. Furthermore, a BCM or DCM in comparison to the continuous conduction mode (CCM)
of operation facilitates a reduced requirement of the primary magnetizing inductance. Lower and upper
boundary for primary magnetizing inductance of 5.17 µH ≤ L
p
≤ 931 µH is identified based on: the
inductance value for which flyback operates in boundary conduction mode and minimum inductance
requirement imposed by the flyback controller. Small magnetizing inductance is desirable because, for a
given geometry and magnetic property of a core material, smaller magnetizing inductance yields: fewer
number of windings, smaller leakage inductance and lower coupling capacitance. The requirement for
the flyback output voltages of +20 V and −5 V in reference to secondary mid-point is determined based
on the recommended turn on/off driving voltages for a 10 kV SiC MOSFET. A high frequency common
mode choke with Y capacitors are placed between the primary winding and control IC to provide a high
impedance path for the common mode currents and redirecting it to ground, respectively.
Transformer design
A major requirement for the flyback transformer is to achieve a low coupling capacitance between the
primary and secondary windings. This coupling capacitance is dependent on the distance between the
primary to secondary windings and the area occupied by the transformer windings on the core. A sig-
nificant and potentially dominant contribution of capacitive coupling is present between the primary and
secondary windings through the transformer core. Graphical representation of the transformer design
is presented in Fig. 4 and the electrical parameters for the designed transformer are summarised in Ta-
ble I. A MnZn toroidal core (TN32/19/13) utilising medium frequency and high permeability magnetic
Primary
Np = 5 turns
Secondary 1
Secondary 2
Ns1 = 8 turns
Ns2 = 2 turns
C iso
2.6 pF
32.2 mm
18.1 mm
Fig. 4: Graphical representation of the de-
signed transformer
Table I: Measured electrical parameters of the flyback trans-
former using a keysight E4990A impedance analyser.
Parameters Values
Isolation Capacitance (C
iso
) 2.6 pF
Primary magnetizing inductance (L
p
) 52.7 µH
Secondary 1 magnetizing inductance (L
s1
) 134 µH
Secondary 2 magnetizing inductance (L
s2
) 8.6 µH
Primary leakage inductance (L
σp
) 3.5 µH
Secondary 1 leakage inductance (L
σs1
) 4.5 µH
Secondary 2 leakage inductance (L
σs2
) 0.3 µH
material (3F3) is chosen for the transformer. A high inductance factor A
L
= L/N
2
of 2270 nH for the
chosen core facilitates with the lower number of windings to achieve the required inductance and thereby
reducing the area occupied by the winding on the transformer core. The number of turns for primary and
secondary windings are determined based on the design constraints imposed by the flyback controller
IC, the desired inductance value and the primary to secondary winding voltage ratio. The primary and
secondary windings are spaced distantly on the core to increase the physical distance between them,
which helps to provide low isolation capacitance but results in an increased leakage inductance of the
transformer due to poor magnetic coupling. The core has an insulation coating rated for 2 kV DC. To
achieve a higher insulation voltage withstand capability a triple insulated wire is utilised for transformer
windings. A layer of insulation tape is placed between the winding and transformer core, lowering
the isolation capacitance further by reducing the coupling through the transformer core. Isolation ca-
pacitance for the designed transformer is measured to be 2.6 pF using a Keysight E4990A impedance
analyser.
Design consideration for primary switch snubber and secondary snubber
Transformer leakage inductance introduces voltage spikes across the primary switch and secondary
diodes during turn off. To protect the flyback switch from over voltages and suppress the voltage spikes
within allowable limits, an RCD snubber with a Zener clamp and an RC snubber is designed for the
switch and diode, respectively [10]. Resistance and capacitance value for RCD snubber is chosen such
that the RC time constant is smaller than the blanking time of the flyback controller IC, within which the
excess energy form the leakage inductance should be dissipated in order to sense the primary winding
voltage correctly. For Zener clamp, the Zener diode is chosen such that the Zener voltage is below the
breakdown voltage of the flyback switch.
Design of a gate driving stage with active Miller clamp functionality
A functional schematic of the gate driving circuitry is presented in Fig. 5. A high-speed gate driver IC
from IXYS (IXDN614) with peak source/sink current capability of 14 A and a low propagation delay
is chosen as a primary driving stage. The output of the driver IC is connected to the gate pad with gate
resistance R
g
. To isolate the control circuit from the high voltage and remove coupling, the gate signals
are transferred optically using an optic fiber link. Preliminary tests showed possibility of unwanted turn
on of the SiC MOSFETs due to the Miller effect under high dv/dt switching transients. To mitigate
this an active Miller clamp circuit is designed and incorporated into the gate drive [11]. Feedback for
DSP
IXDN614
AND
Op�c
V
ref
V
gs
N-MOS
R
g(int)
C
gs
C
gd
C
gd
+
-
V
gs
In+
In-
VCC
GND
VEE
VCC
VEE
VEE
GND
SiC MOSFET
gate signal
VCC = +19 V
VEE = -4.5 V
+
-
GND
GND
R
g
OUT
L
g
C
Reciever
VEE
Fig. 5: Schematic of the gate driving stage with active miller clamp circuit
the Miller clamp circuit is provided by utilizing the gate-source voltage and the input gate signal. A
comparator circuit compares the gate-source voltage with a reference voltage and outputs logic high,
when the sensed voltage reaches below the reference voltage. An additional logic gate is utilized so that
the clamp is activated only when the turn off gate command is received and gate-source voltage is below
the reference voltage. Reference voltage for the clamp is chosen to be lower than the SiC MOSFETs
threshold voltage, meaning that the device turn on/off characteristics are not affected by the Miller clamp
and the clamp is only activated after the MOSFET is turned off. To provide a low impedance path
for the Miller current, an N - channel MOSFET with low on-state resistance of 50 mΩ is used as a
clamping switch. A capacitor with significantly higher capacitance value compared to the device gate-
drain capacitance (C
gd
), is placed between the source of the N - channel MOSFET and ground plane
to prevent rise in clamp voltage due to the flow of Miller current. An image of the gate driver and its
specification are presented in Fig. 6 and Table II, respectively.
142 mm
65
mm
Fig. 6: Image of a designed gate driver circuit
Table II: Gate driver specification
Parameters Values
Nominal input voltage (V
in
) 12 V
Turn-on gate drive voltage (V
gs(on)
) +19 V
Clamp voltage (V
clamp
) −4.5 V
Flyback under voltage lockout 7.5 V
Gate resistance (R
g
) 17 Ω / 25 Ω
