© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for
all other uses, in any current or future media, including reprinting/republishing this material for
advertising or promotional purposes, creating new collective works, for resale or redistribution to
servers or lists, or reuse of any copyrighted component of this work in other works.
Digital Object Identifier (DOI): 10.1109/TIA.2016.2581763
IEEE Transactions on Industry Applications (Volume: 52, Issue: 5, Sept. 2016)
H8 Inverter for Common-Mode Voltage Reduction in Electric Drives
Luca Concari
Davide Barater
Giampaolo Buticchi
Carlo Concari
Marco Liserre
Suggested Citation
L. Concari, D. Barater, G. Buticchi, C. Concari and M. Liserre, "H8 Inverter for Common-Mode Voltage
Reduction in Electric Drives," in IEEE Transactions on Industry Applications, vol. 52, no. 5, pp. 4010-
4019, Sept.-Oct. 2016.
1
H8 Inverter for Common-Mode Voltage reduction in
Electric Drives
Luca Concari, Graduate Student Member, IEEE, Davide Barater, Member, IEEE, Giampaolo Buticchi, Member,
IEEE, Carlo Concari, Member, IEEE, and Marco Liserre, Fellow, IEEE
Abstract—This paper presents a modified two-level three-phase
inverter for the reduction of the leakage current. With respect
to a traditional two-level inverter, the proposed solution reduces
the common-mode voltage, both in amplitude and frequency. Be-
tween the DC source and the traditional three-phase bridge, two
active DC-decoupling devices and a voltage-clamping network
have been added. A dedicated control strategy was developed
adopting a modified Space Vector PWM modulation, oriented
to the reduction of the common-mode voltage. Simulations
showing the good performance of the solution are presented.
A preliminary prototype was developed and experimental results
are presented.
Index Terms—Three-phase, inverter, drive, H8, PWM, space
vector, common-mode voltage, leakage current.
I. INTRODUCTION
Despite the fact that the two-level three-phase inverters are
widely used in electronics, it is well known that they exhibit
poor common-mode voltage (CMV) characteristics. The exis-
tence of several common mode impedance paths between the
converter and the motor/drive frame allows leakage currents
to flow at every CMV variation, so that high pulse-width
modulation frequencies produce high common-mode leakage
currents [1]. In motor drive applications, this may lead to
motor bearing failures, EMI noise that causes inverter drive
trip, or interference with other electronic equipment in the
vicinity [2].
The leakage current problem can be faced by reducing as
much as possible the CMV, both in amplitude and frequency;
ultimately, a constant CMV would not produce such leakage
currents. Passive solutions, adopting passive filters at the
inverter output or input, end up with increased system cost and
size [3]. Depending on the application field, one aspect or the
other may represent a more significant drawback. For example,
size and weight are particularly relevant in aircraft applications
[4], while cost still is significant in more traditional, industrial-
based applications. Furthermore, since these currents flow
through the system enclosure, they are even more relevant
in case of carbon fiber structure used in modern aircraft
applications.
This paper proposes a modified two-level inverter to solve
the problem. It is an upgraded version of [5], where the
same solution was originally presented. Section II presents
a brief state of the art review of converter architectures and
modulation strategies with reduced CMV. In section III a novel
solution is proposed, which takes advantage both from a new
topology and from a dedicated control strategy to reduce the
CMV.
II. STATE OF THE ART
In the past, several authors dealt with the CMV problem
adopting specific control strategies. In [6] and [7] several
PWM strategies are investigated, but they suffer from draw-
backs like not allowing to completely eliminate the CMV,
leading to high current ripple or distortion or even being
not practically feasible. In [8] a combined algorithm with
satisfactory CMV reduction performance is proposed, but it
still exhibits CMV over the PWM period, although reduced
in amplitude and frequency compared to a traditional PWM
modulation. For systems including a rectifier and an inverter,
the CMV excursion can be reduced taking into account the
supply AC voltage waveform for the definition of the SV
pattern [9]. In presence of a fully controllable back-to-back
rectifier/inverter configuration, synchronizing the rectifier and
inverter PWM sequence allows to reduce the number of CMV
pulses within a PWM period [10].
In addition to the traditional three-phase bridge (H6), dif-
ferent architectures have been proposed during the past years.
Here a list of the most relevant ones is presented.
• The Neutral Point Clamped (NPC) inverter, shown in Fig.
1, was proposed for the first time in [11]; since then,
several publications have focused on this topology, which
offers benefits such as reduced switching losses, small
output current ripple, and split supply voltage. Its main
drawback consist in the complexity: more devices and
more driver circuitry are necessary compared to other
architectures and the control turns out to be more complex
as well.
• Another approach to the CMV-related problems consist
in a four-legs inverter like that one in Fig. 2, where a
fourth leg is added to the H6 for controlling the CMV.
Adopting a specific modulation, it can reduce the average
output voltage and the differential mode distortion [12].
Other than in motor drive applications, CMV and common
mode current are relevant in PV generation adopting trans-
formerless conversion. As a matter of fact, there is a common
mode path which includes the panels, the inverter, the grid,
the ground and the stray capacitance between the panels and
their supporting structure. In this context several modulation
techniques have been studied [18] and alternative topologies
proposed with the same aim of reducing the CMV and the
leakage current.
• The topology proposed in [13] and represented in Fig. 3
reduces the CMV and the leakage current, but it has a
great number of components (diodes and switches) which
2
A
B
C
Figure 1. The Neutral Point Clamped inverter [11].
Figure 2. The four-legs inverter [12].
introduce additional switching and conduction losses,
as a consequence the efficiency is lower than in the
conventional three-phase inverter.
• In [14], the authors propose a solution where seven
switches are present (shown in Fig. 4), allowing to
break the leakage current conduction path during the
freewheeling period. It utilizes RCMV-PWM for reducing
the CMV through the elimination of the zero voltage
states. However, it only focuses on leakage current elim-
ination compromising issues such as voltage linearity,
output current ripple, dc-link current ripple and harmonic
distortion.
• The impedance-source converter, depicted in Fig. 5, adds
to the H6 structure an impedance network on the source
side, resulting in a buck-boost inverter. It can be applied
Figure 3. The Two-level Three-phase PV inverter topology [13].
Figure 4. The H7 architecture [14].
Figure 5. The Z-source inverter [15].
PV
Figure 6. The Quasi-Z-source architecture [16].
to every power conversions and to adjustable speed drive,
especially in applications where the input voltage changes
widely. It exhibits good efficiency, can minimize stresses
and size of the motor and performs a higher output power
than a conventional PWM inverter. However, it is suitable
for boost ratio range up to 2, while for higher ratios the
DC/DC boosted PWM inverter is the best configuration.
Furthermore, the presence of a right-hand-plane zero
limits the dynamic response and it cannot be eliminated
by adjusting the Z-source parameters [15], [19].
• The Quasi-Z-source inverter, depicted in Fig. 6, represent
a modified topology with respect to the impedence-source
inverter, with all the advantages of the ZSI and additional
benefits such as a constant input current and less stress
on components, moreover it is suitable for SVPWM
modulations for minimizing the CMV [16].
• A topology called DCM-232 is depicted in Fig. 7. It
makes use of ten switches, six for the H6 and four
(unidirectional, with reverse blocking capability) for a DC
multiplexer with two DC sources (PV panels). Both of
them are disconnected from the DC bus when the zero
vectors are generated, so that the stray capacitance of
the panels remains at a constant value and no leakage
current arises. The solution performs well in terms CMV
and leakage current reduction, however it needs separate
DC sources and it increases the complexity both of the
hardware and of the control because of the presence of
ten switches [17].
PVA
PVB
Figure 7. The DCM-232 inverter [17].
3
III. PROPOSED INVERTER ARCHITECTURE AND
MODULATION
The proposed inverter architecture (shown in Fig. 8) differs
from a traditional H6 for the addition of two active devices
at the DC source side, a capacitor divider and two clamping
diodes. Deriving from a H6 and having a total of eight active
devices, the proposed inverter architecture has been named
”H8”. The two additional active devices, referred to as T 7
and T 8, are placed between the DC source and the three
legs block, and they act as DC-decoupling devices during the
current freewheeling phases. A capacitive divider is placed
on the DC side of the inverter, allowing to obtain voltages
equal to
1
3
V
DC
and
2
3
V
DC
, i.e. the CMV values respectively
during the active odd and even states. In order to ensure an
equal partition of the voltage across the capacitors, an high
impedance (to reduce the power losses) resistive divider was
added in parallel. Two diodes, named D
H
and D
L
, are placed
between the two intermediate points of the divider and the H6
bridge in order to clamp the voltage at the high side or at
the low side of the bridge itself, during the upper or bottom
current freewheeling phases, depending on the case.
The CMV is defined as the average of the voltages between
the inverter outputs and the negative DC source (addressed as
N):
V
CM
=
V
uN
+ V
vN
+ V
wN
3
(1)
Table I summarizes the common mode voltage values at
the inverter output, both for a traditional three-phase inverter
and for the proposed H8 topology. In the case of a traditional
H6, the CMV varies from 0 to V
DC
, with a
1
3
V
DC
step at
every state commutation. The H8 topology only presents two
values for the CMV:
1
3
V
DC
for all the odd states and
2
3
V
DC
for all the even ones. In fact, differently from the H6, the
proposed solution exhibits the same CMV values both during
the active state and the inactive ones. This is possible for the
presence of the DC-decoupling devices (T
7
and T
8
) and of
the voltage-clamping diodes (D
H
and D
L
). Before the high
side current freewheeling phase (state 8, or vector V
8
), when
all the three high side devices in the bridge are on, the upper
DC-decoupling device (T
7
) is switched off and this causes
the diode D
H
to turn on clamping the voltage on the upper
Table I
COMMON-MODE VOLTAGE (V
CM
) VALUES
V
CM
/V
DC
Vectors
Bridge
states
V
u
V
DC
V
v
V
DC
V
w
V
DC
H6
H8 in-
verter
V
1
100 1 0 0 1/3 1/3
V
2
110 1 1 0 2/3 2/3
V
3
010 0 1 0 1/3 1/3
V
4
011 0 1 1 2/3 2/3
V
5
001 0 0 1 1/3 1/3
V
6
101 1 0 1 2/3 2/3
H6
V
7
000 0 0 0 0
V
8
111 1 1 1 1
H8
V
7
000 1/3 1/3 1/3 1/3
V
8
111 2/3 2/3 2/3 2/3
D
L
D
H
T8
V
DC
V
DC
/3
V
DC
/3
+
V
DC
/3
T7
u
v
w
N
P
T3
T4
T5
T6
T1
T2
Figure 8. The proposed H8 inverter topology.
rail of the bridge to
2
3
V
DC
. Similarly, before the low side
current freewheeling phase (state 7, or vector V
7
), when all
the three low side devices in the bridge are on, the bottom
DC-decoupling device (T
8
) is switched off and this causes the
diode D
L
to turn on and therefore the voltage on the bottom
part of the bridge to be
1
3
V
DC
. Then, for both cases, for the
remaining duration of the inactive states the voltage on the
interested side of the bridge maintains those values. Figure 9
shows the eight configurations of the inverter for the eight SV
states.
Since the two clamping diodes ensure the voltage across T
7
and T
8
to be only one third of the total DC bus, devices with
a reduced breakdown voltage can be adopted, reducing than
the additional losses those devices introduce.
In order to force D
H
or D
L
to turn on when the inverter
enters into the zero states, the decoupling devices turn off
is anticipated with respect to the commutation of the bridge
devices. For example, in the transition from state 1 to state
7, first T
8
is switched off, leading to D
L
to turn on (Fig.
10(a)); then T
1
is switched off and after a dead time T
2
is switched on, completing the state commutation. Fig. 10
shows the configurations of the inverter which are put in place
at every transitions from one active states to the following
inactive one. As a matter of fact, during these temporary
phases V
CM
assumes one of the following two values:
V
′
CM
=
1
3
1 +
1
3
+
1
3
V
DC
=
5
9
V
DC
= 0.55V
DC
(2)
V
′′
CM
=
1
3
0 +
2
3
+
2
3
V
DC
=
4
9
V
DC
= 0.44V
DC
(3)
In particular, V
CM
= V
′
CM
in the cases involving odd vectors,
depicted in Fig. 10(a), 10(c) and 10(e), whereas V
CM
= V
′′
CM
in the cases involving even vectors, showed in Fig. 10(b), 10(d)
and 10(f). This implies that CMV is not constant throughout
a PWM period, but it varies from
1
3
V
DC
to
5
9
V
DC
(odd cases)
and from
2
3
V
DC
to
4
9
V
DC
(even cases) at every transition from
an active to an inactive vector. Nevertheless, these variations
are smaller than those typical of traditional solutions. In
particular, for the two cases they result to be:
∆V
′
CM
=
5
9
V
DC
−
1
3
V
DC
= +
2
9
V
DC
= +0.22V
DC
(4)
∆V
′′
CM
=
4
9
V
DC
−
2
3
V
DC
= −
2
9
V
DC
= −0.22V
DC
(5)
It is worth to be noted that D
H
or D
L
turn on only for few
nanoseconds, charging or discharging the stray capacitance of
4
D
L
D
H
T3 T5T1
T4 T6T2
T8
T7
N
P
(a) State 1 (100).
T5
T4T2
D
L
D
H
T3T1
T6
T8
T7
N
P
(b) State 2 (110).
T5T1
T4
D
L
D
H
T3
T6T2
T8
T7
N
P
(c) State 3 (010).
T1
T4 T6
D
L
D
H
T3 T5
T2
T8
T7
N
P
(d) State 4 (011).
T3T1
T6
D
L
D
H
T5
T4T2
T8
T7
N
P
(e) State 5 (001).
T3
T6T2
D
L
D
H
T5T1
T4
T8
T7
N
P
(f) State 6 (101).
T3
D
L
D
H
T5T1
T4 T6T2
T8
T7
N
P
(g) State 7 (000).
T4 T6T2
D
L
D
H
T3 T5T1
T8
T7
N
P
(h) State 8 (111).
Figure 9. Configurations of the H8 inverter for the eight Space Vector states.
Devices are depicted in black if they are on, in gray if they are off. Current
conduction through anti-parallel diodes are neglected for simplicity.
the devices, therefore not causing a significant unbalance in
the voltage divider. However, they are passive devices, so they
need a current flowing from the DC side to the AC side in
order to turn on. In case of zero current, this does not occur,
hence the CMV deteriorates.
The modulation adopted for the control of the inverter is
a novel Space Vector (SV) strategy, specifically developed
in conjunction with the H8 architecture, with the aim to
achieve an almost constant CMV (as previously discussed,
±
2
9
V
DC
variations are unavoidable) and performing single leg
commutations. In the following, this strategy will be addressed
as Constant Common-Mode Voltage Space Vector (CCMV-
SV), however it can only be applied for modulation indexes
lower than 0.5 (Fig. 13(b) and 13(c)). In order to overcome
to the linearity range limitation, the system can switch to a
different control strategy when a higher modulation index is
needed. In such a case, a Near State Space Vector (NS-SV)
is adopted, since this extends the modulation index range up
to
√
3/2 (see Fig. 13(d)). Compared to CCMV-SV, NS-SV
performs worse in terms of CMV, but in conjunction with
the proposed topology it ensures advantages over conventional
three-phase inverters. The following two subsections discuss
in further detail the two developed modulation strategies.
T3 T5
T8
DC
V
3
1
D
L
D
H
T1
T4 T6T2
T7
N
P
(a) Leading phase between state
1 and state 7.
T5
T4T2
DC
V
3
2
D
L
D
H
T3T1
T6
T8
T7
N
P
(b) Leading phase between state
2 and state 8.
T5T1
T4
T8
DC
V
3
1
D
L
D
H
T3
T6T2
T7
N
P
(c) Leading phase between state
3 and state 7.
T4 T6
DC
V
3
2
D
L
D
H
T3 T5T1
T2
T8
T7
N
P
(d) Leading phase between state
4 and state 8.
T3
T6
T8
DC
V
3
1
D
L
D
H
T5T1
T4T2
T7
N
P
(e) Leading phase between state
5 and state 7.
T3
T6T2
DC
V
3
2
D
L
D
H
T5T1
T4
T8
T7
N
P
(f) Leading phase between state
6 and state 8.
Figure 10. Configurations of the H8 inverter during transitions from active
to inactive states. Devices are depicted in black if they are on, in gray if
they are off. Current conduction through anti-parallel diodes are neglected for
simplicity.
A. Modulation index smaller than 0.5: CCMV-SV modulation
In order to maintain a constant CMV at the inverter output,
this SV strategy only makes use of those vectors exhibiting the
same V
CM
. Table I shows the ratios between V
CM
and V
DC
for all the eight SV states. As a matter of fact, odd active
vectors (V
1
, V
3
and V
5
) exhibit V
CM
=
1
3
V
DC
, while even
active vectors (V
2
, V
4
and V
6
) have V
CM
=
2
3
V
DC
. This is
also true considering the H6 and, indeed, several modulations
were proposed in literature attempting to keep common-mode
voltage constant by using only a set of vectors that exhibit
the same V
CM
[6]. Nevertheless, those modulations do not
make use of inactive vectors (V
7
, V
8
), and this results in
simultaneous commutations of more than one bridge leg. On
the contrary, adopting the H8 architecture, V
CM
values of the
inactive vectors, thanks to the DC decoupling, can match them
of the active states. In this context, it is possible to obtain the
same CMV values with all the odd vectors (V
1
, V
3
, V
5
and
V
7
), or with all the even ones (V
2
, V
4
, V
6
and V
8
). As already
mentioned in Sec. III, at every transition from an active state
to an inactive one, CMV becomes equal to
4
9
V
DC
or to
5
9
V
DC
(see Eq. 2 and 3), leading to a ±
2
9
V
DC
variation of CMV.
The reference vector in the α − β plane is synthesized by
the use of the two nearest odd or even vectors with the proper
modulated duration, plus the proper inactive state fulfilling the
remaining time in the PWM period. Applying this scheme, the
points which can be synthesized are included in two equilateral
triangles having vertexes on the applied active vectors (see
Fig. 13(b) and 13(c)). The maximum modulation index which
![Figure 5. The Z-source inverter [15].](/figures/figure-5-the-z-source-inverter-15-2wtywbpo.webp)
